Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware construction language embedded in Scala that enables generating synthesizable Verilog via the FIRRTL and CIRCT compiler infrastructure. It provides a rich set of abstractions—including Modules, Bundles, Vecs, Registers, Memories, and state machines—along with a standard library of reusable circuit generators (FIFOs, arbiters, counters, LFSRs, decoders) and a built-in verification framework with assertion macros, LTL sequences, and simulation backends (Verilator, VCS). The project is actively maintained by the CHIPS Alliance and is widely used in both academia and industry for RTL design and FPGA/ASIC development. The architecture is a layered compiler pipeline: user-written Scala code defines hardware via the Chisel DSL, which is elaborated into an internal IR (CHIRRTL), then lowered to FIRRTL, and finally compiled to SystemVerilog using the external CIRCT toolchain (firtool). The codebase is split into a core library (`core`), a deprecated FIRRTL compiler (`firrtl`), simulation infrastructure (`svsim`), a Scala compiler plugin for automatic naming and cloneType generation, and a comprehensive test suite. Despite the dual Scala 2/3 maintenance and some deprecated APIs, the code is well-structured, extensively tested, and demonstrates high craftsmanship in macro-based DSL embedding, type-safe connection operators, and logic minimization algorithms.
The openwifi repository provides a full-stack IEEE 802.11 (Wi-Fi) implementation for Software Defined Radio (SDR) hardware, specifically targeting Xilinx Zynq/ZynqMP SoCs with AD9361/AD9364 RF transceivers. It consists of a Linux kernel driver (split into multiple modules for OFDM, TX/RX interfaces, and side-channel processing) and user-space tools for hardware configuration, FPGA bitstream loading, and Wi-Fi interface management. The system supports standard Wi-Fi modes (AP, STA, ad-hoc, monitor) and experimental features like Channel State Information (CSI) extraction, packet injection/fuzzing, and radar sensing. The build system uses Buildroot to generate bootable SD card images, and the project includes extensive documentation for experimentation and hardware bring-up.
Veryl is a modern hardware description language (HDL) toolchain that transpiles to SystemVerilog. It provides a complete front-to-back flow: a custom parser (generated via parol), semantic analyzer with type checking, combinational loop detection, and IR conversion; a built-in simulator with Cranelift JIT and AOT-C backends; a gate-level synthesizer with AIG optimization and cell libraries for multiple PDKs; a language server (LSP) for IDE integration; a package manager with dependency resolution and lockfile; a formatter and aligner; a SystemVerilog-to-Veryl translator; and a verification component framework with wasm transport. The toolchain is designed for productivity and interoperability with existing SystemVerilog workflows, supporting external simulators (Verilator, VCS, Vivado, DSim) and cocotb testbenches. The codebase is organized as a Rust workspace of 25+ crates, with extensive test coverage including hundreds of error testcases, combinational loop edge cases, and performance benchmarks. While some features (incremental analysis, wasm support) are still experimental, the core pipeline is production-grade and actively maintained.
IOb-cache is an open-source, highly configurable cache IP core written in Verilog, designed for FPGA and ASIC integration. It features a pipelined architecture that allows one request per clock cycle (read and write), supports configurable set-associativity (direct-mapped to k-way), multiple replacement policies (LRU, PLRU_MRU, PLRU_TREE), and both write-through and write-back write policies. The front-end can connect via IOb, AXI-Lite, or Wishbone interfaces, while the back-end supports IOb or AXI4. A built-in cache controller provides software-accessible registers for performance monitoring (hit/miss counters), cache invalidation, and write-through buffer status. The project is managed through the Py2hwsw Python framework, which generates the full hardware and software stack, including simulation wrappers, synthesis constraints, and testbench software. The repository includes comprehensive documentation (LaTeX user guide), CI/CD pipelines (simulation, FPGA build, linting), and FuseSoC compatibility for easy reuse. Although primarily a hardware design, the testbench software is written in C and exercises the cache through memory-mapped I/O. The core has been peer-reviewed (published in Algorithms journal) and is integrated into the IOb-SoC system. Current limitations include a TODO note about fixing testbenches and improving documentation. The hardware code is well-structured and modular, with reusable components such as the replacement policy and cache controller blocks.
Apio is a command-line interface (CLI) tool designed to streamline FPGA hardware development workflows. It acts as a wrapper and manager for open-source EDA toolchains (Yosys, Nextpnr, Verilator, GTKWave) and hardware drivers, supporting multiple FPGA architectures (ICE40, ECP5, GOWIN, XILINX) and over 80 development boards. The tool automates the full lifecycle of FPGA projects, including initialization, linting, synthesis, place-and-route, simulation, and bitstream upload to hardware. Architecturally, Apio follows a modular design with a Click-based CLI layer that delegates heavy build tasks to a SCons subprocess. Communication between the CLI and SCons is handled via Protocol Buffers to avoid global state sharing. The codebase includes robust package management for downloading and installing toolchains, cross-platform support for Linux, macOS, and Windows, and a comprehensive test suite using pytest. It is a professional-grade tool with strong engineering practices, including CI/CD pipelines and semantic versioning. Technical drift is moderate due to the volatile nature of SCons APIs and the reliance on external toolchain versions. There is also a noted inconsistency in Python version usage (mixing 3.9 compatibility checks with 3.10+ match statements). However, the repository is actively maintained with recent commits and a healthy issue resolution rate. The codebase is suitable for reuse in FPGA tooling projects, particularly the package management and IPC patterns.
This is a comprehensive FPGA HDL reference design repository from Analog Devices, providing reusable IP cores and complete project templates for interfacing ADI data converters (ADCs/DACs), RF transceivers, and mixed-signal devices with Xilinx, Intel, and Lattice FPGAs. The architecture is modular: a library of parameterized AXI peripherals (e.g., axi_dmac, axi_clkgen, axi_pwm_gen), JESD204B/C link layer cores, SPI engine framework, I3C controller, and utility modules (clock-domain crossing, data packing, FIFOs) are assembled via Tcl-based block designs and Make-driven build scripts into carrier-specific reference designs. The repository is actively maintained with CI checks, extensive documentation (Sphinx, register maps, timing constraints), and testbenches for key blocks. It is not a software application or data research repository; it is a hardware design framework for FPGA-based acquisition and generation systems.
PeakRDL is a CLI toolchain for control/status register (CSR) generation centered around the SystemRDL 2.0 language. It compiles register descriptions from SystemRDL or imported formats (e.g., IP-XACT) and exports synthesizable SystemVerilog RTL, C headers, UVM register models, HTML documentation, and more. The architecture is a pluggable CLI: a core dispatcher loads subcommands (built-in: dump, globals, preprocess) and external exporter/importer plugins via setuptools entry points or TOML config. Input processing handles SystemRDL compilation, parameterized components, and element arrays. The codebase demonstrates strong Python engineering with modular configuration schema validation, argument file expansion with environment variable support, and a clean plugin discovery mechanism.
This repository implements a cycle-accurate NES/Famicom console on FPGA, targeting the MiSTer platform. The core is written in Verilog/SystemVerilog with some VHDL, integrating a 6502 CPU (T65 core), PPU with composite video output, APU with expansion audio support, and dozens of cartridge mappers (MMC1-5, VRC1-7, FDS, Namco163, Sunsoft, etc.). It provides a complete hardware video/audio pipeline including scanlines, gamma correction, scandoubling, HQ2x scaling, and HDMI output. The system supports save states, cheat codes, zapper light gun, multiplayer adapters, and the Family BASIC keyboard. The codebase is well-structured with a modular mapper interface and a generic savestate bus pattern, though it is tightly coupled to the MiSTer platform (Cyclone V FPGA, HPS interface). It is an actively maintained core in the MiSTer ecosystem, with frequent releases and community contributions.
RVX is a fully functional RISC-V RV32I microcontroller IP core written in synthesizable Verilog, targeting FPGAs (specifically Digilent Arty A7 and Cmod A7 boards). It implements the RV32I base ISA v2.1 plus the Zicsr extension and Machine-Level ISA v1.13. The core includes a custom system bus (`rvx_bus`) that can be parameterized with an arbitrary number of memory-mapped slaves, and a set of peripherals: UART, GPIO, SPI, and machine timer (`mtime`/`mtimecmp`). The repository provides complete example projects for bare-metal and FreeRTOS, including board-specific wrapper modules, constraint files, and TCL scripts for Vivado project creation. The software examples use CMake with the RISC-V GCC toolchain and the `libsteel` hardware abstraction library. A comprehensive verification suite covers all RV32I instructions via RISC-V Architecture Test programs, alongside Cocotb-based peripheral tests and a Verilator simulation framework with C++ harness. The bus interface uses a simple request/response handshake with write strobes, which is clean but non-standard (not AXI/Wishbone). The core is a single-monolithic file (~1300 lines) with a 4-state FSM and no pipelining, making it compact but harder to modify. Overall, the repository is a well-documented, professionally structured open-source hardware project with strong testing practices, suitable for FPGA-based embedded systems education or low-complexity control applications.
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.
Icestudio is an open-source graphical FPGA design and programming environment. It allows users to create digital circuits by dragging, dropping, and wiring blocks representing logic elements, I/O, constants, memory, and code. The tool then compiles the design into Verilog, runs the open-source FPGA toolchain (yosys, nextpnr, apio) to generate a bitstream, and uploads it to a wide variety of Lattice iCE40 and ECP5 boards. The application is built as a desktop app using NW.js (Node.js + Chromium) with an AngularJS 1.x frontend, JointJS for diagramming, and a custom plugin system for extensibility. It supports over 60 FPGA boards, includes a package manager (iceHub) for block collections, a serial terminal plugin, a board editor, and an integrated toolchain shell. The codebase is mature but relies on several deprecated technologies (AngularJS, NW.js, Grunt) and lacks automated tests, making modernization risky. Key reusable elements include the event bus, plugin manager, orthogonal wire router, and file system indexer.