UltraJSON is a high-performance JSON encoder/decoder library for Python, implemented entirely in C with Python bindings. It provides drop-in replacements for Python's standard json module (ujson.dumps, ujson.loads, ujson.dump, ujson.load) and offers configuration options for ASCII encoding, HTML character escaping, forward slash escaping, indentation, sorting keys, NaN/Infinity handling, and customizable separators. The library's core architecture consists of a hand-optimized C state machine for decoding and a recursive encoder that handles Python objects via a type-context system. It bundles a copy of the double-conversion library for precise floating-point serialization and uses a stack-first, heap-later buffer allocation strategy. Despite being in maintenance-only mode due to architectural security concerns, the codebase exhibits strong craftsmanship: meticulous memory management, comprehensive UTF-8 validation, support for surrogate pairs, fuzz testing with ref-count verification, and compatibility with CPython's free-threaded builds. The repository also includes extensive tests, benchmarks, and CI for multiple architectures and Python implementations (CPython, PyPy, GraalPy).
Av1an is a hyper-scalable video encoding framework written in Rust, designed to parallelize encoding of AV1 (and other codecs) by splitting videos into scenes, encoding each scene independently, and concatenating the results. It supports multiple encoders (aomenc, SVT-AV1, rav1e, x264, x265, vpx) and provides advanced features like target quality (iterative probing to achieve a desired VMAF/SSIMULACRA2/Butteraugli score), VapourSynth integration for frame-accurate input and metric calculations, and scene detection via av-scenechange. The architecture is a classic library+binary workspace: `av1an-core` contains all encoding logic, chunk management, metrics, interpolation, and concatenation, while the `av1an` binary provides a CLI interface with extensive options for chunking methods, encoder parameters, zones, and resume capabilities. The system relies heavily on external tools (ffmpeg, mkvmerge, vspipe, encoder binaries) and uses a broker-based worker pool for parallel encoding with progress bars and Ctrl+C handling. The codebase is well-tested with integration tests that run actual encodes, and includes a dedicated interpolation module with eight methods (linear, natural cubic spline, Fritsch-Carlson, PCHIP, quadratic, cubic polynomial, Catmull-Rom, Akima) that is self-contained and reusable. While the project demonstrates strong engineering practices (modular design, extensive tests, CI/CD), it carries some technical debt: heavy use of nightly Rust features, global state via OnceCell, many unwrap/expect calls, and tight coupling to external tool versions. The repository is actively maintained with recent commits and a responsive issue tracker.
This repository provides a comprehensive, production-grade Field-Oriented Control (FOC) library for Permanent Magnet Synchronous Motors (PMSM) targeting embedded microcontrollers (STM32G4, CH32V3). It is written in C and organized into modular algorithm files covering coordinate transforms (Clarke, Park), PWM modulation (SVPWM, SPWM), multiple control strategies (PID, LADRC, SMC, STA), sensor feedback (encoder, Hall, sensorless observers like HFI, SMO, NLFO), and advanced features (MTPA, field weakening, harmonic suppression, cogging calibration, dead-time compensation, feedforward, disturbance observer, parameter identification). The architecture is driven by interrupt-based control loops (high-frequency current loop, low-frequency state machine, and serial communication loop) with compile-time configuration via macro switches and user-supplied hardware abstraction layers. The repository also includes open-source hardware designs (schematic and PCB for a robot-joint motor driver), a QT-based host computer application, Simulink simulation models, and a complete STM32G4 example project. Although the library contains multiple coexisting versions and v4.0.0 is partially incomplete, the core modules are well-crafted, independently reusable, and demonstrate advanced control theory implementation suitable for robotics, drones, industrial servos, and electric tools.
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.