This repository provides a library of reusable VHDL IP cores for FPGA design, focusing on fixed-point arithmetic, basic building blocks (FIFOs, RAM, clock crossing), and interfaces (SPI, I2C, UART, AXI). Each component is parameterized, well-documented, and includes testbenches for verification. The library is designed for portability across FPGA toolchains and includes tutorials for integration with major tools like Vivado, Quartus, and others.
Queuelib is a Python library providing persistent and in-memory queue data structures. It implements FIFO, LIFO, priority, and round-robin queues with disk-based storage options for durability. The library is dependency-free, using only the Python standard library, and is designed for scenarios requiring reliable queuing such as web crawlers. Architecture consists of modular components: base queue classes in queue.py, priority queue in pqueue.py, and round-robin queue in rrqueue.py. Disk-based queues manage data through chunk files (FIFO) or single files (LIFO) with careful bookkeeping to survive process restarts. The priority and round-robin queues use a factory pattern to decouple queue logic from storage implementation, enabling flexibility.
lockfree is a header-only C++11 library providing lock-free data structures for concurrent programming. It offers both single-producer single-consumer (SPSC) and multi-producer multi-consumer (MPMC) variants of queues, ring buffers, bipartite buffers, and priority queues. The library is designed for use across a wide spectrum of systems from deeply embedded to HPC, featuring no dynamic allocation and optimized for high performance. Architecture-wise, it's organized into spsc/ and mpmc/ namespaces with each data structure having separate header and implementation files, aggregated through lockfree.hpp. The implementation uses atomic operations and clever algorithms to achieve lock-free behavior without mutexes.
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.