The openwifi repository provides a full-stack IEEE 802.11 (Wi-Fi) implementation for Software Defined Radio (SDR) hardware, specifically targeting Xilinx Zynq/ZynqMP SoCs with AD9361/AD9364 RF transceivers. It consists of a Linux kernel driver (split into multiple modules for OFDM, TX/RX interfaces, and side-channel processing) and user-space tools for hardware configuration, FPGA bitstream loading, and Wi-Fi interface management. The system supports standard Wi-Fi modes (AP, STA, ad-hoc, monitor) and experimental features like Channel State Information (CSI) extraction, packet injection/fuzzing, and radar sensing. The build system uses Buildroot to generate bootable SD card images, and the project includes extensive documentation for experimentation and hardware bring-up.
This is a comprehensive FPGA HDL reference design repository from Analog Devices, providing reusable IP cores and complete project templates for interfacing ADI data converters (ADCs/DACs), RF transceivers, and mixed-signal devices with Xilinx, Intel, and Lattice FPGAs. The architecture is modular: a library of parameterized AXI peripherals (e.g., axi_dmac, axi_clkgen, axi_pwm_gen), JESD204B/C link layer cores, SPI engine framework, I3C controller, and utility modules (clock-domain crossing, data packing, FIFOs) are assembled via Tcl-based block designs and Make-driven build scripts into carrier-specific reference designs. The repository is actively maintained with CI checks, extensive documentation (Sphinx, register maps, timing constraints), and testbenches for key blocks. It is not a software application or data research repository; it is a hardware design framework for FPGA-based acquisition and generation systems.
This repository is Xilinx's fork of QEMU, a full-system and user-mode emulator/virtualizer. It provides machine emulation via dynamic binary translation (TCG) and hardware acceleration through KVM, Xen, HVF, and other accelerators. The codebase includes a vast array of device models (CPUs, interrupt controllers, storage, network, graphics, timers, etc.), a block layer for storage backends, live migration for VM state transfer, and QMP/HMP monitoring interfaces. The architecture is highly modular with the QEMU Object Model (QOM), coroutine-based async I/O, and a plugin API. It also supports user-mode emulation for Linux and BSD syscalls. This is purely an application repo; there is no data science or research code. The Xilinx fork adds extensive device models for Xilinx FPGAs and SoCs (Versal, ZynqMP, etc.), making it especially relevant for embedded developers. The code is actively maintained with recent commits and issue triage, and while the sheer size introduces some technical debt, the overall engineering quality is high.
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.