$ show analogdevicesinc/hdl
This is a comprehensive FPGA HDL reference design repository from Analog Devices, providing reusable IP cores and complete project templates for interfacing ADI data converters (ADCs/DACs), RF transceivers, and mixed-signal devices with Xilinx, Intel, and Lattice FPGAs. The architecture is modular: a library of parameterized AXI peripherals (e.g., axi_dmac, axi_clkgen, axi_pwm_gen), JESD204B/C link layer cores, SPI engine framework, I3C controller, and utility modules (clock-domain crossing, data packing, FIFOs) are assembled via Tcl-based block designs and Make-driven build scripts into carrier-specific reference designs. The repository is actively maintained with CI checks, extensive documentation (Sphinx, register maps, timing constraints), and testbenches for key blocks. It is not a software application or data research repository; it is a hardware design framework for FPGA-based acquisition and generation systems.
The LLM identified 5 files worth highlighting for reuse:
A configurable DMA controller supporting AXI4 memory-mapped and streaming interfaces, with scatter-gather, 2D transfers, cyclic mode, and external synchronization. It is the central data movement engine used across nearly all projects, and its modular design (separate source/destination modules, request arbiter, response handler) makes it a reusable building block for any FPGA data acquisition or generation system.
The JESD204B/C receiver link layer core, implementing lane alignment, frame alignment, elastic buffer, error monitoring, and ILAS capture. It is the foundation for high-speed converter interfaces and is reused across dozens of projects. The design is vendor-neutral (with separate Xilinx/Intel wrappers) and includes comprehensive testbenches for CGS, frame alignment, and scrambler verification.
A configurable SPI execution engine that supports command-based SPI transactions with offload capability (autonomous data capture to FIFO). It is part of the SPI Engine framework used in many precision ADC projects. The module is self-contained, parameterizable (data width, CS delay, clock divider), and can be extracted for any project requiring high-throughput SPI control or data streaming.
A generic multi-bit synchronizer for clock domain crossing, using double-flop synchronization with configurable number of stages and reset behavior. It is a fundamental building block used throughout the repository and is directly reusable in any FPGA design requiring safe CDC for control signals.
A generic AXI4-Lite slave interface that provides a standardized register map access mechanism for all ADI IP cores. It handles address decoding, read/write transactions, and interrupt generation. This module is the backbone of software-configurable IP and can be reused in any custom AXI peripheral design.