This is a comprehensive FPGA HDL reference design repository from Analog Devices, providing reusable IP cores and complete project templates for interfacing ADI data converters (ADCs/DACs), RF transceivers, and mixed-signal devices with Xilinx, Intel, and Lattice FPGAs. The architecture is modular: a library of parameterized AXI peripherals (e.g., axi_dmac, axi_clkgen, axi_pwm_gen), JESD204B/C link layer cores, SPI engine framework, I3C controller, and utility modules (clock-domain crossing, data packing, FIFOs) are assembled via Tcl-based block designs and Make-driven build scripts into carrier-specific reference designs. The repository is actively maintained with CI checks, extensive documentation (Sphinx, register maps, timing constraints), and testbenches for key blocks. It is not a software application or data research repository; it is a hardware design framework for FPGA-based acquisition and generation systems.