This repository provides an ESPHome external component and a Home Assistant custom component for controlling Mitsubishi heat pumps via the CN105 serial interface. The core component implements a full climate controller with dual setpoint support, multiple operating modes (heat, cool, heat_cool, dry, fan_only), fan speeds, swing modes, remote temperature integration, and a wide array of sensors (compressor frequency, power, kWh, outside temperature, error codes, etc.). It communicates with the heat pump over UART at 2400 baud using a reverse-engineered protocol with checksum validation and cyclic request scheduling. The Home Assistant proxy component dynamically adjusts the UI to show single or dual setpoint sliders based on the active mode, fixes Auto mode behavior, and supports advanced features like coordinator single-target mode for multi-zone systems. The codebase is well-structured with standalone reusable modules for frame parsing, protocol encoding/decoding, request scheduling, and temperature conversion, supported by a comprehensive unit test suite and CI pipeline. The repository includes example configurations for various microcontrollers (ESP32, Xiao, M5Stack) and deployment scenarios, making it a mature and practical solution for integrating Mitsubishi heat pumps into smart home systems.
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.