$ show pConst/basic_verilog
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.
The LLM identified 6 files worth highlighting for reuse:
Parameterized single-bit clock-domain-crossing module for strobes/pulses. Implements the classic multi-flop synchronizer plus pulse edge detection to pass one-clock-wide events between unrelated clock domains. Fully self-contained, vendor-agnostic, synthesizable, with an accompanying testbench (cdc_strobe_tb.sv) and instantiation template in comments. This is the pattern every digital design needs and it is safely extractable into any FPGA project.
Single-clock FIFO built from inferred block RAM with read/write pointer management; configurable depth and FWFT (first-word fall-through) behavior. Ships with initialization memory files, a testbench, and RAM/depth parameterization that works across Xilinx, Intel, and Gowin flows. Demonstrates the standard circular-buffer-with-flag-generation pattern used in virtually all FPGA datapaths. Easily extracted as a standalone FIFO IP.
Round-robin/priority encoder optimized to skip inactive requestors in a single combinational step, rather than sequentially rotating through all inputs. A non-obvious arbitration pattern for shared buses, multi-channel DMA, and packet schedulers. Self-contained with a performance testbench (round_robin_performance_enc_tb.sv) and parameterized input width; extract and reuse directly.
PRBS generator/checker pair supporting standard ITU-T O.150 LFSR polynomials, used for high-speed link BER testing and pattern injection in FPGA bring-up. Combines transmit-side LFSR generation with receive-side checking/error flagging in one parameterized module, with testbench. Self-contained and vendor-agnostic — a common recurring need in SerDes and transceiver validation.
Header file of parameterized functions for binary-to-Gray and Gray-to-binary conversion, used in clock-domain-crossing counters and encoders. Pure combinational logic, zero resource cost, and directly includable in any Verilog/SystemVerilog project. Demonstrates the idiomatic packed-array function approach for reusable RTL logic rather than module instantiation.
Safely combines multiple asynchronous reset inputs and generates synchronized, correctly-deasserted reset pulses for each target clock domain. This is the canonical asynchronous-assert/synchronous-deassert reset distribution pattern that is notoriously easy to get wrong and rarely implemented cleanly in-house. From the Altera Cookbook, but the pattern is vendor-agnostic and the module is a standalone leaf ideal for extraction into any FPGA/ASIC reset tree.