This repository provides Hardware Abstraction Layers (HAL) for Raspberry Pi RP2040 and RP235x microcontrollers. It consists of separate HAL crates for each microcontroller family (rp2040-hal, rp235x-hal), a shared common library (rp-hal-common), binary info generation for picotool (rp-binary-info), examples demonstrating peripheral usage, and on-target tests. The HALs expose peripherals like GPIO, UART, SPI, I2C, PWM, PIO, USB, and more through safe Rust abstractions using the typestate pattern and embedded-hal traits. The architecture follows embedded Rust best practices with clear separation of concerns. Each HAL crate can be used as a dependency in embedded projects. Key innovations include a bidirectional DMA abstraction for full-duplex communication, split UART reader/writer peripherals preventing data races, a glitchless clock configuration system with typestate safety, and a comprehensive PIO driver for programmable I/O. The project is actively maintained with regular commits, CI workflows for multiple platforms, and issue triage. While some code duplication exists between the HALs due to architectural differences, ongoing efforts rationalize shared code into rp-hal-common. The HALs are suitable for production use in embedded applications targeting these microcontrollers. Examples demonstrate real-world usage patterns like ADC with DMA, USB device implementation, multicore FIFO communication, and low-power dormant mode. Dependencies are current with the embedded Rust ecosystem (embedded-hal 1.0.0-beta, fugit, etc.), and the project avoids deprecated patterns. The binary info generation utility is a reusable component that could apply to any embedded Rust project requiring picotool compatibility.
SwiftIO is a Swift framework for microcontrollers that provides an easy-to-use interface for hardware peripherals. It abstracts low-level hardware details into Swift classes, allowing developers to interact with GPIO, ADC, PWM, timers, communication protocols (I2C, SPI, UART), and more without dealing with complex register manipulation. The library is structured into a C layer (CSwiftIO) for direct hardware access and a Swift layer that wraps this functionality in a safe, idiomatic API. It emphasizes error handling through Swift's Result type and provides consistent patterns for resource management and peripheral interaction.
RVX is a fully functional RISC-V RV32I microcontroller IP core written in synthesizable Verilog, targeting FPGAs (specifically Digilent Arty A7 and Cmod A7 boards). It implements the RV32I base ISA v2.1 plus the Zicsr extension and Machine-Level ISA v1.13. The core includes a custom system bus (`rvx_bus`) that can be parameterized with an arbitrary number of memory-mapped slaves, and a set of peripherals: UART, GPIO, SPI, and machine timer (`mtime`/`mtimecmp`). The repository provides complete example projects for bare-metal and FreeRTOS, including board-specific wrapper modules, constraint files, and TCL scripts for Vivado project creation. The software examples use CMake with the RISC-V GCC toolchain and the `libsteel` hardware abstraction library. A comprehensive verification suite covers all RV32I instructions via RISC-V Architecture Test programs, alongside Cocotb-based peripheral tests and a Verilator simulation framework with C++ harness. The bus interface uses a simple request/response handshake with write strobes, which is clean but non-standard (not AXI/Wishbone). The core is a single-monolithic file (~1300 lines) with a 4-state FSM and no pipelining, making it compact but harder to modify. Overall, the repository is a well-documented, professionally structured open-source hardware project with strong testing practices, suitable for FPGA-based embedded systems education or low-complexity control applications.
This repository is a comprehensive bare-metal microcontroller programming guide, providing step-by-step examples from minimal firmware to a full embedded web server with a device dashboard. The code targets ARM Cortex-M and RISC-V microcontrollers (STM32, TI TM4C, RP2040, ESP32-C3, nRF52840, etc.) and uses only GCC, a datasheet, and the Mongoose networking library. The architecture is bare-metal, single-threaded with an event loop in the webserver step; it demonstrates direct register manipulation, interrupt handling, UART, SysTick, clock configuration, printf retargeting via newlib syscalls, CMSIS integration, and Ethernet with built-in TCP/IP (MIP). The repository also includes reusable project templates for blinky, CLI, and LittleFS filesystem. Despite being educational, the code is production-quality and follows embedded best practices such as non-blocking timers, hardware abstraction layers (hal.h), and modular startup code.
This repository provides ESPHome firmware configurations and custom components to control LoctekMotion/FlexiSpot standing desks via Home Assistant. The core functionality is implemented as two custom ESPHome sensor components: `loctekmotion_desk_height` for reading desk height from a 7-segment display protocol over UART, and `loctekmotion_desk_command` for detecting keypad button presses. The primary entry points are the YAML package files (`packages/office-desk-esp32.yaml` and `packages/office-desk-esp32-passthrough.yaml`) which wire up UART communication, GPIO control for the screen wake pin (PIN20), and expose cover, button, switch, and number entities to Home Assistant. The architecture is a typical ESPHome device: a single microcontroller (ESP32/ESP8266) running the ESPHome firmware, communicating with the desk controller via a 9600 baud UART serial link. The repo also contains archived Arduino and Raspberry Pi implementations, but the active development is focused on the ESPHome components. It is a well-structured IoT integration project with CI/CD, linting, and test compilation for multiple board variants.
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.