$ show rafaelcalcada/rvx
RVX is a fully functional RISC-V RV32I microcontroller IP core written in synthesizable Verilog, targeting FPGAs (specifically Digilent Arty A7 and Cmod A7 boards). It implements the RV32I base ISA v2.1 plus the Zicsr extension and Machine-Level ISA v1.13. The core includes a custom system bus (`rvx_bus`) that can be parameterized with an arbitrary number of memory-mapped slaves, and a set of peripherals: UART, GPIO, SPI, and machine timer (`mtime`/`mtimecmp`). The repository provides complete example projects for bare-metal and FreeRTOS, including board-specific wrapper modules, constraint files, and TCL scripts for Vivado project creation. The software examples use CMake with the RISC-V GCC toolchain and the `libsteel` hardware abstraction library. A comprehensive verification suite covers all RV32I instructions via RISC-V Architecture Test programs, alongside Cocotb-based peripheral tests and a Verilator simulation framework with C++ harness. The bus interface uses a simple request/response handshake with write strobes, which is clean but non-standard (not AXI/Wishbone). The core is a single-monolithic file (~1300 lines) with a 4-state FSM and no pipelining, making it compact but harder to modify. Overall, the repository is a well-documented, professionally structured open-source hardware project with strong testing practices, suitable for FPGA-based embedded systems education or low-complexity control applications.
The LLM identified 3 files worth highlighting for reuse:
This is the system bus interconnect module, parameterizable by number of device ports, each with configurable start address and region size. Address decoding uses a mask-based scheme (region size must be power of two). The interface uses request/response handshaking with separate read and write channels. This module is self-contained, well-parameterized, and could be reused in any RISC-V or other bus-based digital design requiring memory-mapped slave selection. It demonstrates clean modular design with explicit synthesis attributes for width inference.
Provides two functions to initialize simulation RAM from hex files: `init_h32` (reads a hex file with memory addresses and data, writes to a 32-bit wide memory array) and `init_binary` (reads binary file directly). Also includes a `write_ram` function for setting memory during simulation. These functions are generic and can be reused in any Verilator-based testbench for a memory-mapped design. The code is well-structured with error handling and file I/O, and demonstrates a solid pattern for loading program images into simulation models.
The bootstrap assembly file for bare-metal RISC-V programs. It sets up the global pointer (`gp`), initializes the stack pointer (`sp`) to the end of the `.data` section, clears the trap interrupt vector by writing to `mtvec`, and jumps to `main`. This is a minimal, correct, and reusable entry point for any RV32I bare-metal project. It is self-contained and follows common RISC-V startup conventions, making it easy to extract for other project templates.