RVX is a fully functional RISC-V RV32I microcontroller IP core written in synthesizable Verilog, targeting FPGAs (specifically Digilent Arty A7 and Cmod A7 boards). It implements the RV32I base ISA v2.1 plus the Zicsr extension and Machine-Level ISA v1.13. The core includes a custom system bus (`rvx_bus`) that can be parameterized with an arbitrary number of memory-mapped slaves, and a set of peripherals: UART, GPIO, SPI, and machine timer (`mtime`/`mtimecmp`). The repository provides complete example projects for bare-metal and FreeRTOS, including board-specific wrapper modules, constraint files, and TCL scripts for Vivado project creation. The software examples use CMake with the RISC-V GCC toolchain and the `libsteel` hardware abstraction library. A comprehensive verification suite covers all RV32I instructions via RISC-V Architecture Test programs, alongside Cocotb-based peripheral tests and a Verilator simulation framework with C++ harness. The bus interface uses a simple request/response handshake with write strobes, which is clean but non-standard (not AXI/Wishbone). The core is a single-monolithic file (~1300 lines) with a 4-state FSM and no pipelining, making it compact but harder to modify. Overall, the repository is a well-documented, professionally structured open-source hardware project with strong testing practices, suitable for FPGA-based embedded systems education or low-complexity control applications.
This repository implements a Field-Programmable Gate Array (FPGA) based emulator for Nintendo Game Boy and Game Boy Color systems, specifically targeting the Analogue Pocket handheld console. The design consists of hardware description language (Verilog/VHDL) modules that replicate the original hardware components including a Z80-compatible CPU core (T80), memory controllers, video display subsystem, four-channel audio processing unit, input handling, cartridge interface with various Memory Bank Controller (MBC) implementations, save state functionality, and real-time clock support. The architecture follows a modular approach with clear separation of concerns between subsystems, interconnected through well-defined interfaces. The project demonstrates significant effort in achieving hardware-level accuracy while incorporating modern features like save states, fast forwarding, and custom palettes. While the codebase shows signs of active maintenance and ongoing development, it remains tightly coupled to the target FPGA platform (Cyclone V) and associated Intel/Altera toolchain, which limits immediate portability to other hardware platforms.