$ show budude2/openfpga-GBC
This repository implements a Field-Programmable Gate Array (FPGA) based emulator for Nintendo Game Boy and Game Boy Color systems, specifically targeting the Analogue Pocket handheld console. The design consists of hardware description language (Verilog/VHDL) modules that replicate the original hardware components including a Z80-compatible CPU core (T80), memory controllers, video display subsystem, four-channel audio processing unit, input handling, cartridge interface with various Memory Bank Controller (MBC) implementations, save state functionality, and real-time clock support. The architecture follows a modular approach with clear separation of concerns between subsystems, interconnected through well-defined interfaces. The project demonstrates significant effort in achieving hardware-level accuracy while incorporating modern features like save states, fast forwarding, and custom palettes. While the codebase shows signs of active maintenance and ongoing development, it remains tightly coupled to the target FPGA platform (Cyclone V) and associated Intel/Altera toolchain, which limits immediate portability to other hardware platforms.
The LLM identified 3 files worth highlighting for reuse:
The T80 CPU core is a well-known, parameterizable Z80-compatible processor implementation in VHDL. It is highly modular, with separate files for ALU, microcode, registers, and packaging, allowing easy extraction for use in other projects requiring a compatible CPU core. The design demonstrates skill through its configurability via generics to match specific processor variants (like the Game Boy's LR35902) and its clean separation of concerns.
This file implements the Game Boy Color sound APU with four channels (two square waves, programmable wave, noise) and stereo output. It features a well-structured design with separate processes for each channel, a mixer, envelope/length/sweep handling, and integrated save state support. The component showcases skill in accurately modeling complex audio hardware while maintaining modularity and clear signal organization, making it a valuable reference for audio subsystem design in FPGA projects.
The save state controller provides a reusable infrastructure for saving and restoring system state in FPGA designs. It uses a standardized bus interface to interact with individual save state registers (eReg_Savestate components) distributed across subsystems. The design demonstrates skill through its scalable approach to state management, clear separation between controller and storage elements, and handling of complex synchronization requirements for consistent state capture/restore.