thehardwarestore.ai

simdjson is a high-performance C++ JSON parsing library that uses SIMD instructions (AVX2, AVX-512, NEON, RVV, etc.) to parse and validate JSON at multi-gigabyte-per-second speeds. It provides two primary APIs: a DOM API (`simdjson::dom`) that builds a complete in-memory tree, and an On-Demand API (`simdjson::ondemand`) that performs lazy, forward-only parsing for streaming and large-document use cases. The library also includes a builder API for JSON serialization, compile-time JSON parsing via C++26 reflection, JSON Pointer/Path support, NDJSON/JSON-sequence streaming, and a single-header amalgamated distribution. The codebase is organized around a two-stage pipeline: stage 1 performs SIMD-accelerated structural indexing and UTF-8 validation, and stage 2 builds the DOM tape or drives the on-demand iterator. Runtime CPU dispatch selects the best implementation for the host architecture, with fallbacks for non-SIMD platforms. The repository is a mature, production-grade library used by major projects (Node.js, ClickHouse, etc.) and is backed by an extensive test suite, fuzzing harnesses, and cross-architecture CI. It is primarily an application/library rather than a data-research repository, though it contains benchmark and research-oriented components (e.g., performance modeling, static reflection experiments).

Ibex is a production-quality open-source 32-bit RISC-V CPU core designed for embedded control applications. It provides a highly configurable, synthesizable core written in SystemVerilog with support for RISC-V ISA extensions (I, E, M, C, B) and security features like PMP, lockstep, and data-independent timing. The core features a modular architecture with separate functional units, a sophisticated configuration system via YAML/Python, and extensive verification infrastructure including UVM testbenches, formal proofs, and co-simulation with Spike ISS. It is actively maintained and used in real silicon designs including OpenTitan.

The KFR library is a high-performance C++ framework for digital signal processing (DSP) and audio applications. It provides optimized implementations of FFT/DFT, filter design (FIR/IIR), sample rate conversion, audio file I/O (supporting WAV, FLAC, MP3, AIFF, CAF, etc.), SIMD-accelerated mathematical operations, and tensor/multi-dimensional array operations. The library is designed for real-time processing and scientific computing, with architecture-specific optimizations for x86 SIMD, ARM NEON, and RISC-V RVV, and runtime dispatch for multiarchitecture support. Key architectural features include a header-only design (with optional separate compilation), expression templates for lazy evaluation and operator fusion, a portable SIMD abstraction layer, and a tensor system with NumPy interoperability. The library is used in production by scientific collaborations such as LIGO, Virgo, and KAGRA for gravitational-wave signal processing, benchmarked against FFTW. It employs a dual licensing model (GPLv2+/commercial) and requires C++20 for compilation. The codebase demonstrates strong engineering practices through reusable components such as the SIMD vector abstraction (vec<T, N>), expression template system, tensor class, and audio data handling unit. These components are self-contained, exhibit non-obvious skill in C++ template metaprogramming, and can be extracted for use in other projects with minimal modification. The library is actively maintained, with recent commits and CI/CD pipelines, and shows low technical drift by keeping pace with modern C++ standards and hardware advancements.

iPXE is an open-source network boot firmware that provides a full PXE implementation with enhanced capabilities. It operates as a pre-boot environment, replacing or supplementing traditional BIOS/UEFI PXE ROMs. The firmware supports booting over HTTP/HTTPS, iSCSI, Fibre Channel over Ethernet (FCoE), AoE, InfiniBand, and wireless networks, with full TLS 1.2 support including modern cipher suites (ECDHE, GCM, X25519, P-256/P-384). It includes a built-in command-line shell, scripting engine, interactive menus, and extensive hardware drivers for network cards, USB controllers, and storage devices across x86, ARM, RISC-V, LoongArch, and s390x architectures. The architecture is modular and table-driven: drivers, protocols, commands, and startup functions are registered via compile-time tables (e.g., `__pci_driver`, `__net_protocol`, `__command`), enabling a highly configurable build. The core uses an interface/refcount pattern for object-oriented-like composition, with reference-counted objects and asynchronous data transfer via `struct interface`. The codebase is well-structured with clear separation between architecture-specific code (under `src/arch/`), platform interfaces (EFI, BIOS, Linux userspace, SBI), and generic core logic. A comprehensive test suite (over 50 unit tests plus Wycheproof vectors) validates cryptographic primitives, network protocols, and data structures. Key entry points include `src/core/main.c` (generic boot flow), EFI application entry (`efiprefix.c`), BIOS PXE ROM entry, and Linux userspace binary. The firmware is typically embedded into option ROMs, UEFI drivers, or bootable images. External dependencies are minimal—the firmware runs directly on hardware or under a hypervisor, relying only on platform firmware services (UEFI, BIOS, SBI) for low-level operations.

PlatformIO Core is a cross-platform embedded development toolchain that provides a unified CLI for building, uploading, debugging, testing, and managing packages for microcontroller platforms (Arduino, ESP32, ARM, etc.). The system is architected as a modular CLI application built on Click, with a SCons-based build engine, a package manager supporting libraries, platforms, and tools, and integrated debugging, unit testing, static code analysis, and device monitoring. Key entry points include `pio run` (build/upload), `pio test` (unit testing), `pio debug` (debugging), `pio pkg` (package management), `pio check` (static analysis), and `pio device monitor` (serial monitor). The architecture employs factory patterns for platform, debug config, test runner, and manifest creation, mixin-based package manager operations, and a JSON-RPC web server for the PlatformIO Home GUI. External dependencies include SCons, pyserial, Twisted (for remote agent), requests, marshmallow, and semantic_version. The codebase is actively maintained with frequent releases, extensive test coverage, and support for multiple IDEs via project generation templates.

IronOS is embedded firmware for a family of portable soldering irons (TS100, TS80/P, TS101, Pinecil, Pinecil V2, MHP30, Sequre S60/S60P/T55/S99). The firmware runs on three distinct SoC architectures — STM32F103 (Cortex-M3), GD32VF103 (RISC-V), and Bouffalo BL702 (RISC-V) — behind a single board-support abstraction. It implements PID temperature control of the soldering tip via PWM, thermocouple uV-to-temperature conversion with cold-junction compensation, USB-PD (FUSB302/FUSB302B/HUB238/FS2711) and Quick Charge 3.0 power negotiation, accelerometer/hall-effect-based motion detection for sleep, an OLED menu UI, and a full BLE GATT stack on Pinecil V2. The core control loop is: ADC samples tip thermocouple voltage (with PWM holdoff timing) -> gain/op-amp compensation and lookup-table interpolation to Celsius -> PID controller -> PWM duty to the heating element, with input voltage/current monitoring for wattage budgeting and thermal runaway protection.

This repository provides educational materials for a hands-on course on building a RISC-V CPU core from scratch. The core is implemented in Transaction-Level Verilog (TL-Verilog) and is designed to run on the Makerchip online IDE. The repository contains a starting-point shell (risc-v_shell.tlv) with a simple test program that sums 1 to 9, and a reference solutions file (risc-v_solutions.tlv) that hides the full implementation. The library (lib/risc-v_shell_lib.tlv) includes reusable, parameterized components such as a register file, data memory, instruction decoder, ALU, and a sophisticated CPU visualization module. The code is modular, uses M4 macros for assembly and configuration, and is well-structured for educational purposes. While the repository is not a standalone application, it effectively demonstrates digital logic design and CPU microarchitecture concepts in a simulation environment.

This repository implements a compiler-based optimization framework for zero-knowledge virtual machines (zkVMs), specifically targeting OpenVM and SP1. Its core innovation is Automatic Precompile Synthesis (APC), which analyzes execution traces of RISC-V guest programs and synthesizes optimized constraint systems (symbolic machines) that drastically reduce proof cost—achieving up to 9x column reduction and 88x constraint reduction on complex operations. The system combines profile-guided optimization (PGO), a sophisticated constraint solver with range reasoning and rule-based rewriting, and an optional Lean4 verified optimizer via FFI. The architecture is a multi-crate Rust workspace with a CLI (`powdr_openvm_riscv`) orchestrating a staged pipeline: generate APCs from execution profiles, select the best candidates using PGO metrics, setup the prover with the selected APCs, execute the program, and generate proofs. It supports CPU and GPU (CUDA) backends, and includes extensive benchmarking infrastructure with nightly regression analysis and a web-based APC effectiveness viewer. Bus interaction handling is abstracted via a `BusMap` and adapter pattern, making the optimization logic VM-agnostic. While primarily an application, the repository has strong research character: it includes domain-specific formal methods (Lean4, Datalog rules), empirical constraint detection, and a large corpus of snapshot tests documenting optimizer outputs. It is actively maintained with CI pipelines, but depends on several tightly coupled forks (OpenVM, SP1) and pinned nightly Rust toolchains, posing moderate technical drift risk.

RVX is a fully functional RISC-V RV32I microcontroller IP core written in synthesizable Verilog, targeting FPGAs (specifically Digilent Arty A7 and Cmod A7 boards). It implements the RV32I base ISA v2.1 plus the Zicsr extension and Machine-Level ISA v1.13. The core includes a custom system bus (`rvx_bus`) that can be parameterized with an arbitrary number of memory-mapped slaves, and a set of peripherals: UART, GPIO, SPI, and machine timer (`mtime`/`mtimecmp`). The repository provides complete example projects for bare-metal and FreeRTOS, including board-specific wrapper modules, constraint files, and TCL scripts for Vivado project creation. The software examples use CMake with the RISC-V GCC toolchain and the `libsteel` hardware abstraction library. A comprehensive verification suite covers all RV32I instructions via RISC-V Architecture Test programs, alongside Cocotb-based peripheral tests and a Verilator simulation framework with C++ harness. The bus interface uses a simple request/response handshake with write strobes, which is clean but non-standard (not AXI/Wishbone). The core is a single-monolithic file (~1300 lines) with a 4-state FSM and no pipelining, making it compact but harder to modify. Overall, the repository is a well-documented, professionally structured open-source hardware project with strong testing practices, suitable for FPGA-based embedded systems education or low-complexity control applications.

This repository contains the RISC-V Advanced Core-Local Interrupt Controller (ACLIC) specification document, which defines extensions for fast interrupt handling in RISC-V processors. It includes detailed AsciiDoc specification chapters, example handler assembly code for various interrupt processing models (software dispatcher, fast handler, and push-pop handler), a test plan for architectural verification, and build infrastructure (Makefile, CI workflows) to produce PDF and HTML outputs. The repo is primarily a specification artifact with supporting code examples intended for hardware implementers and compiler developers. It is not a standalone software application but a technical reference with reusable assembly patterns.