$ show riscv/riscv-fast-interrupt
This repository contains the RISC-V Advanced Core-Local Interrupt Controller (ACLIC) specification document, which defines extensions for fast interrupt handling in RISC-V processors. It includes detailed AsciiDoc specification chapters, example handler assembly code for various interrupt processing models (software dispatcher, fast handler, and push-pop handler), a test plan for architectural verification, and build infrastructure (Makefile, CI workflows) to produce PDF and HTML outputs. The repo is primarily a specification artifact with supporting code examples intended for hardware implementers and compiler developers. It is not a standalone software application but a technical reference with reusable assembly patterns.
The LLM identified 4 files worth highlighting for reuse:
An assembly implementation of a RISC-V interrupt software dispatcher for the ACLIC extension. It saves context, reads mcause, calls the appropriate handler from a table indexed by interrupt ID, uses mtopsi to claim and raise priority threshold, and restores context before mret. This pattern demonstrates nested preemption support and efficient dispatch, serving as a reusable template for any RISC-V ACLIC system.
A minimal assembly template for a fast, non-preemptible interrupt handler in RISC-V. It saves mepc and mistatus on the stack, enables interrupts, executes the handler body, then restores and returns via mret. The macro definitions for XLEN-dependent register sizes (sr/lr) make it easily adaptable to RV32 or RV64. Ideal as a starting point for simple, low-latency interrupt service routines.
An example handler for the Smip extension, which provides automatic push/pop of context. It uses mipopret instruction instead of explicit register save/restore, significantly reducing handler code size. The sequence of saving mepc and mistatus before enabling interrupts demonstrates the correct pattern for preemptible handlers with hardware stacking support. This pattern is directly reusable in ACLIC implementations with Smip.
A comprehensive test plan for verifying the RISC-V CLIC (Core-Local Interrupt Controller) architectural specification. It defines deterministic test sequences, pseudo-code templates, and coverage objectives for various modes (M-mode, S-mode, with/without delegation, thresholds, level/priority, etc.). The test organization and macro-based framework (RVMODEL_*) can be reused as a template for planning verification of other RISC-V extensions or interrupt controllers.