Chisel is a hardware construction language (DSL) embedded in Scala. It provides a rich set of abstractions (Module, Bundle, Reg, Mem, UInt, SInt, Bool, Vec, Clock, When) for describing synchronous digital circuits at the register-transfer level. The system compiles these circuit descriptions into an intermediate representation (FIRRTL/CIRRTL) and then uses the CIRCT compiler framework to generate synthesizable SystemVerilog. It also includes a comprehensive simulation framework (svsim, ChiselSim) for verification on Verilator or VCS, formal verification capabilities (LTL properties), and a standard library of reusable hardware components (counters, queues, FIFOs, arbiters, decoders, PRNGs). The architecture is a multi-stage compiler pipeline: user code elaboration, FIRRTL IR conversion, and CIRCT-based code generation. It relies on external tools like firtool, Verilator, Espresso, and Slang. The codebase is actively maintained with a clear versioning history (7.x), but carries significant technical debt from a deprecated FIRRTL package, an ongoing Scala 2 to Scala 3 migration, and a large surface of experimental features.
PeakRDL is a CLI toolchain for control/status register (CSR) generation centered around the SystemRDL 2.0 language. It compiles register descriptions from SystemRDL or imported formats (e.g., IP-XACT) and exports synthesizable SystemVerilog RTL, C headers, UVM register models, HTML documentation, and more. The architecture is a pluggable CLI: a core dispatcher loads subcommands (built-in: dump, globals, preprocess) and external exporter/importer plugins via setuptools entry points or TOML config. Input processing handles SystemRDL compilation, parameterized components, and element arrays. The codebase demonstrates strong Python engineering with modular configuration schema validation, argument file expansion with environment variable support, and a clean plugin discovery mechanism.
This repository provides educational materials for a hands-on course on building a RISC-V CPU core from scratch. The core is implemented in Transaction-Level Verilog (TL-Verilog) and is designed to run on the Makerchip online IDE. The repository contains a starting-point shell (risc-v_shell.tlv) with a simple test program that sums 1 to 9, and a reference solutions file (risc-v_solutions.tlv) that hides the full implementation. The library (lib/risc-v_shell_lib.tlv) includes reusable, parameterized components such as a register file, data memory, instruction decoder, ALU, and a sophisticated CPU visualization module. The code is modular, uses M4 macros for assembly and configuration, and is well-structured for educational purposes. While the repository is not a standalone application, it effectively demonstrates digital logic design and CPU microarchitecture concepts in a simulation environment.
This repository contains the hardware design files, CAD models (F3D, STEP, STL), and comprehensive documentation for the ERCF v2 (Enraged Rabbit Carrot Feeder version 2), a multi-material filament changer for 3D printers, primarily the Voron ecosystem. It is not a software application in the traditional sense—there is no executable code beyond configuration and scripting guides for Klipper firmware (Happy Hare plugin). The repo provides stl files for printing mechanical parts, CAD source files for modification, detailed assembly manuals (PDF), and step-by-step tutorials for hardware calibration, Klipper installation, and slicer setup. It also includes recommended optional add-ons (buffer, filament cutter, rewinder) and user-contributed modifications. The project is well-structured with clear directory layouts and extensive community support, evidenced by high stars and active issue tracking.
This repository provides board support packages for the LiteX open-source FPGA SoC builder. It contains over 150 platform definitions (pinouts, connectors, toolchain setup) and corresponding target scripts that assemble a complete SoC (CPU, memory, peripherals) for each FPGA board. The architecture is a collection of Python modules organized into `litex_boards/platforms/` and `litex_boards/targets/`, with each target being a standalone script that can be invoked via `python -m litex_boards.targets.<board> --build --load`. The system supports a wide range of FPGA families (Xilinx, Lattice, Intel/Altera, Gowin, Efinix, CologneChip) and integrates with the broader LiteX ecosystem (LiteDRAM, LiteEth, LitePCIe, etc.) for memory controllers, networking, and high-speed interfaces. Key entry points are the `main()` functions in each target file, which use `LiteXArgumentParser` for CLI argument handling and `Builder` for bitstream generation. The repository is community-maintained under litex-hub and includes CI scripts for consistency checks, board inventory generation, and regression tests.
This repository is an open-source hardware reference design for the Framework Laptop 13, containing 3D CAD models (STEP, STL, DXF), 2D mechanical drawings, partial schematics, pinout tables, and 3D-printable case files. It is not a software application or data research project; it is a collection of design files enabling repair, customization, and third-party accessory development. The repository is organized by subsystem (mainboard, display, battery, hinges, touchpad, webcam, etc.) with detailed README documentation. The only software component is a GitHub Actions workflow for CLA compliance. The repository demonstrates high craftsmanship in hardware documentation with standardized pinout tables and modular printable case designs. It is actively maintained with recent commits and an active issue tracker.
This repository contains the open-source hardware design files for the 'dumbpad', a customizable 4x4 mechanical macropad with support for rotary encoders, OLED displays, and RGB LEDs. It is a hardware design repository, not a software application. The repo includes multiple PCB variants (Eagle and KiCad formats) with different features: through-hole switches, hotswap sockets, low-profile Gateron switches, per-key RGB, and OLED displays. Also included are 3D-printable case designs (STL and SketchUp files), Gerber manufacturing files, and VIA configuration JSON. The designs are modular, with reusable KiCad footprints and a standard keyboard matrix pattern. The project is actively maintained with several community-contributed variants. No firmware source code is present; the macropad is intended to run QMK firmware, which is maintained separately.
This repository contains the open-source hardware design for the DEV-G2-NANO development board, created by Theta Machines LLC. It is a KiCad v10 project (rev 0.1) targeting an NXP i.MX RT1171 dual-core MCU (Cortex-M7/M4) with a companion Kinetis KL26 for DAPLink debug. The board integrates a MAYA-W166-00B Wi-Fi/BT module, an LSM6DSV IMU, an LIS2MDL magnetometer, and an RTMC-G2-4IQ48 motion controller, making it suitable for robotics and real-time control applications. The design is organized into hierarchical schematics (power, configuration, user I/O) with custom symbols and footprints. It is licensed under CERN-OHL-P-2.0, allowing commercial use. Note: This is a hardware design repository, not software; the analysis criteria have been adapted accordingly.