Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware construction language embedded in Scala that enables generating synthesizable Verilog via the FIRRTL and CIRCT compiler infrastructure. It provides a rich set of abstractions—including Modules, Bundles, Vecs, Registers, Memories, and state machines—along with a standard library of reusable circuit generators (FIFOs, arbiters, counters, LFSRs, decoders) and a built-in verification framework with assertion macros, LTL sequences, and simulation backends (Verilator, VCS). The project is actively maintained by the CHIPS Alliance and is widely used in both academia and industry for RTL design and FPGA/ASIC development. The architecture is a layered compiler pipeline: user-written Scala code defines hardware via the Chisel DSL, which is elaborated into an internal IR (CHIRRTL), then lowered to FIRRTL, and finally compiled to SystemVerilog using the external CIRCT toolchain (firtool). The codebase is split into a core library (`core`), a deprecated FIRRTL compiler (`firrtl`), simulation infrastructure (`svsim`), a Scala compiler plugin for automatic naming and cloneType generation, and a comprehensive test suite. Despite the dual Scala 2/3 maintenance and some deprecated APIs, the code is well-structured, extensively tested, and demonstrates high craftsmanship in macro-based DSL embedding, type-safe connection operators, and logic minimization algorithms.
IOb-cache is an open-source, highly configurable cache IP core written in Verilog, designed for FPGA and ASIC integration. It features a pipelined architecture that allows one request per clock cycle (read and write), supports configurable set-associativity (direct-mapped to k-way), multiple replacement policies (LRU, PLRU_MRU, PLRU_TREE), and both write-through and write-back write policies. The front-end can connect via IOb, AXI-Lite, or Wishbone interfaces, while the back-end supports IOb or AXI4. A built-in cache controller provides software-accessible registers for performance monitoring (hit/miss counters), cache invalidation, and write-through buffer status. The project is managed through the Py2hwsw Python framework, which generates the full hardware and software stack, including simulation wrappers, synthesis constraints, and testbench software. The repository includes comprehensive documentation (LaTeX user guide), CI/CD pipelines (simulation, FPGA build, linting), and FuseSoC compatibility for easy reuse. Although primarily a hardware design, the testbench software is written in C and exercises the cache through memory-mapped I/O. The core has been peer-reviewed (published in Algorithms journal) and is integrated into the IOb-SoC system. Current limitations include a TODO note about fixing testbenches and improving documentation. The hardware code is well-structured and modular, with reusable components such as the replacement policy and cache controller blocks.
PeakRDL is a CLI toolchain for control/status register (CSR) generation centered around the SystemRDL 2.0 language. It compiles register descriptions from SystemRDL or imported formats (e.g., IP-XACT) and exports synthesizable SystemVerilog RTL, C headers, UVM register models, HTML documentation, and more. The architecture is a pluggable CLI: a core dispatcher loads subcommands (built-in: dump, globals, preprocess) and external exporter/importer plugins via setuptools entry points or TOML config. Input processing handles SystemRDL compilation, parameterized components, and element arrays. The codebase demonstrates strong Python engineering with modular configuration schema validation, argument file expansion with environment variable support, and a clean plugin discovery mechanism.