Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware construction language embedded in Scala that enables generating synthesizable Verilog via the FIRRTL and CIRCT compiler infrastructure. It provides a rich set of abstractions—including Modules, Bundles, Vecs, Registers, Memories, and state machines—along with a standard library of reusable circuit generators (FIFOs, arbiters, counters, LFSRs, decoders) and a built-in verification framework with assertion macros, LTL sequences, and simulation backends (Verilator, VCS). The project is actively maintained by the CHIPS Alliance and is widely used in both academia and industry for RTL design and FPGA/ASIC development. The architecture is a layered compiler pipeline: user-written Scala code defines hardware via the Chisel DSL, which is elaborated into an internal IR (CHIRRTL), then lowered to FIRRTL, and finally compiled to SystemVerilog using the external CIRCT toolchain (firtool). The codebase is split into a core library (`core`), a deprecated FIRRTL compiler (`firrtl`), simulation infrastructure (`svsim`), a Scala compiler plugin for automatic naming and cloneType generation, and a comprehensive test suite. Despite the dual Scala 2/3 maintenance and some deprecated APIs, the code is well-structured, extensively tested, and demonstrates high craftsmanship in macro-based DSL embedding, type-safe connection operators, and logic minimization algorithms.