$ show chipsalliance/chisel
Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware construction language embedded in Scala that enables generating synthesizable Verilog via the FIRRTL and CIRCT compiler infrastructure. It provides a rich set of abstractions—including Modules, Bundles, Vecs, Registers, Memories, and state machines—along with a standard library of reusable circuit generators (FIFOs, arbiters, counters, LFSRs, decoders) and a built-in verification framework with assertion macros, LTL sequences, and simulation backends (Verilator, VCS). The project is actively maintained by the CHIPS Alliance and is widely used in both academia and industry for RTL design and FPGA/ASIC development. The architecture is a layered compiler pipeline: user-written Scala code defines hardware via the Chisel DSL, which is elaborated into an internal IR (CHIRRTL), then lowered to FIRRTL, and finally compiled to SystemVerilog using the external CIRCT toolchain (firtool). The codebase is split into a core library (`core`), a deprecated FIRRTL compiler (`firrtl`), simulation infrastructure (`svsim`), a Scala compiler plugin for automatic naming and cloneType generation, and a comprehensive test suite. Despite the dual Scala 2/3 maintenance and some deprecated APIs, the code is well-structured, extensively tested, and demonstrates high craftsmanship in macro-based DSL embedding, type-safe connection operators, and logic minimization algorithms.
The LLM identified 5 files worth highlighting for reuse:
Implements the `:<`, `:>=`, `:<>=`, `:#=`, `:%=` connection operators with orientation-aware alignment. Supports waiving, squeezing, and excluding members before connection. The `ConnectableAlignment` class recursively walks records and vectors to compute compatibility, providing a fluent API for precise hardware wiring. This pattern is self-contained and could be extracted for use in other HDL DSLs or formal verification tools.
Defines `TruthTable` and `BitSet` abstractions for representing and minimizing Boolean functions. Includes `QMCMinimizer` (Quine-McCluskey with Petrick's method) and `EspressoMinimizer` wrappers. The `BitSet` class provides set operations (union, intersect, subtract, overlap, cover) on don't-care patterns. This is a self-contained logic minimization library that could be reused for any Boolean function minimization task.
Provides a typeclass-based `DataView` pattern that enables lightweight, zero-cost views between different Chisel `Data` types (e.g., Scala tuples, Seq, subtype Bundles). Supports both total and partial mappings with runtime validation. The `DataProduct` typeclass enables generic iteration over fields. This pattern is highly reusable for any system requiring structural type conversion without copying, especially in hardware simulation and testing.
Implements Linear Temporal Logic (LTL) within Chisel as an embedded DSL. Provides `Sequence` and `Property` types with operators for delay, and, or, intersect, implication, eventually, always, past, and repeat. Uses opaque `Bool` wrappers and FIRRTL intrinsics for lowering. This is a self-contained formal verification DSL that could be adopted for other hardware languages or formal analysis tools.
Provides a generic directed graph implementation with BFS, strongly connected components, linearization (topological order), edge addition/removal, and path finding. Used internally for FIRRTL transform dependency resolution. Despite being in a deprecated package, the graph is self-contained and could be extracted as a standalone library for any dependency graph analysis.