IOb-cache is an open-source, highly configurable cache IP core written in Verilog, designed for FPGA and ASIC integration. It features a pipelined architecture that allows one request per clock cycle (read and write), supports configurable set-associativity (direct-mapped to k-way), multiple replacement policies (LRU, PLRU_MRU, PLRU_TREE), and both write-through and write-back write policies. The front-end can connect via IOb, AXI-Lite, or Wishbone interfaces, while the back-end supports IOb or AXI4. A built-in cache controller provides software-accessible registers for performance monitoring (hit/miss counters), cache invalidation, and write-through buffer status. The project is managed through the Py2hwsw Python framework, which generates the full hardware and software stack, including simulation wrappers, synthesis constraints, and testbench software. The repository includes comprehensive documentation (LaTeX user guide), CI/CD pipelines (simulation, FPGA build, linting), and FuseSoC compatibility for easy reuse. Although primarily a hardware design, the testbench software is written in C and exercises the cache through memory-mapped I/O. The core has been peer-reviewed (published in Algorithms journal) and is integrated into the IOb-SoC system. Current limitations include a TODO note about fixing testbenches and improving documentation. The hardware code is well-structured and modular, with reusable components such as the replacement policy and cache controller blocks.