IOb-cache is an open-source, highly configurable cache IP core written in Verilog, designed for FPGA and ASIC integration. It features a pipelined architecture that allows one request per clock cycle (read and write), supports configurable set-associativity (direct-mapped to k-way), multiple replacement policies (LRU, PLRU_MRU, PLRU_TREE), and both write-through and write-back write policies. The front-end can connect via IOb, AXI-Lite, or Wishbone interfaces, while the back-end supports IOb or AXI4. A built-in cache controller provides software-accessible registers for performance monitoring (hit/miss counters), cache invalidation, and write-through buffer status. The project is managed through the Py2hwsw Python framework, which generates the full hardware and software stack, including simulation wrappers, synthesis constraints, and testbench software. The repository includes comprehensive documentation (LaTeX user guide), CI/CD pipelines (simulation, FPGA build, linting), and FuseSoC compatibility for easy reuse. Although primarily a hardware design, the testbench software is written in C and exercises the cache through memory-mapped I/O. The core has been peer-reviewed (published in Algorithms journal) and is integrated into the IOb-SoC system. Current limitations include a TODO note about fixing testbenches and improving documentation. The hardware code is well-structured and modular, with reusable components such as the replacement policy and cache controller blocks.
This repository contains the complete design files, firmware, and assembly instructions for the Redox ergonomic split mechanical keyboard. It is not a software application in the traditional sense but rather an open-source hardware project delivering PCB Gerber/KiCad files, 3D-printable case STLs, precompiled QMK firmware hex files, and detailed build guides for both wired (Rev1.0) and wireless (Rev1.0W, Rev2.0WHS) variants. The code aspect consists of firmware configuration and custom KiCad footprints for keyboard components. The repository serves as a distribution hub for makers to manufacture their own Redox keyboard, with instructions for flashing via avrdude, ST-Link/Docker, and supports multiple firmware ecosystems (QMK, ZMK, KMK). The primary value is in the hardware design and documentation, not in runtime software.
This repository is the complete open-source hardware and software stack for the Roboto Origin bipedal robot, formerly known as Atom01. It is a hybrid monorepo covering mechanical design (CAD files, 3D printing, BOMs), electronics (PCB designs, firmware for a USB2CAN board), low-level ROS2 control (motor drivers, IMU, camera, inference), simulation and reinforcement learning training (roboparty_train with Isaac Sim/MuJoCo and PPO/AMP algorithms), navigation (LiDAR localization, UWB, path planning), and XR teleoperation. The repository is organized into multiple modules, each with its own build system (CMake, Zephyr, Python). The dominant character is an application (a robot system), but it includes a substantial data_research component in the training module where RL policies are trained using motion capture data. The codebase is well-structured, actively maintained, and provides a complete recipe for building and deploying a humanoid robot from scratch.
This repository is an open-source hardware reference design for the Framework Laptop 13, containing 3D CAD models (STEP, STL, DXF), 2D mechanical drawings, partial schematics, pinout tables, and 3D-printable case files. It is not a software application or data research project; it is a collection of design files enabling repair, customization, and third-party accessory development. The repository is organized by subsystem (mainboard, display, battery, hinges, touchpad, webcam, etc.) with detailed README documentation. The only software component is a GitHub Actions workflow for CLA compliance. The repository demonstrates high craftsmanship in hardware documentation with standardized pinout tables and modular printable case designs. It is actively maintained with recent commits and an active issue tracker.
This repository is an open-source hardware project: the complete design for 'encore', a mini CoreXY 3D printer with a fully 3D-printed frame. Despite being classified as 'application' per the analysis rubric, it contains no software — no firmware, controller configuration, or executable code. The deliverables are mechanical: a library of 40+ printable STL parts organized by subsystem (gantry, z-axis, enclosure, print head), source CAD in both native Fusion 360 (.f3z) and neutral STEP (.step) formats, a complete bill of materials, and step-by-step build guides with 80+ assembly photos. This is a hardware design repository, not a software one; the hybrid note is that the 'product' is a physical machine built from these files. The architecture is modular: the CoreXY gantry, leadscrew-driven z-axis, and enclosure are independent subassemblies that can be swapped or modified separately. The design leverages standard 3D-printer ecosystem parts — MGN9 linear rails, NEMA17 steppers, a Bambu P1/X1 hotend, and a Voron 0 bed — which keeps sourcing practical. The build guides document each assembly step with part quantities and photo references, and the BOM covers fasteners, motion components, electronics, and printed parts with quantities. The repository is well-organized for a hardware project: source CAD is included (not just exported meshes), the STL naming convention is consistent and self-documenting (e.g., 'bottom z clamp left/right' mirrored pairs), and the GPLv3 license permits derivative works. Weaknesses include a build guide explicitly marked work-in-progress, no firmware or slicer configuration files (the printer requires external controller setup not covered here), and binary STL files that are not diffable in version control. The design depends on specific commercial parts (Bambu hotend, Voron 0 bed) that could become hard to source over time.
Icestudio is an open-source graphical FPGA design and programming environment. It allows users to create digital circuits by dragging, dropping, and wiring blocks representing logic elements, I/O, constants, memory, and code. The tool then compiles the design into Verilog, runs the open-source FPGA toolchain (yosys, nextpnr, apio) to generate a bitstream, and uploads it to a wide variety of Lattice iCE40 and ECP5 boards. The application is built as a desktop app using NW.js (Node.js + Chromium) with an AngularJS 1.x frontend, JointJS for diagramming, and a custom plugin system for extensibility. It supports over 60 FPGA boards, includes a package manager (iceHub) for block collections, a serial terminal plugin, a board editor, and an integrated toolchain shell. The codebase is mature but relies on several deprecated technologies (AngularJS, NW.js, Grunt) and lacks automated tests, making modernization risky. Key reusable elements include the event bus, plugin manager, orthogonal wire router, and file system indexer.
This repository contains the open-source hardware design for the DEV-G2-NANO development board, created by Theta Machines LLC. It is a KiCad v10 project (rev 0.1) targeting an NXP i.MX RT1171 dual-core MCU (Cortex-M7/M4) with a companion Kinetis KL26 for DAPLink debug. The board integrates a MAYA-W166-00B Wi-Fi/BT module, an LSM6DSV IMU, an LIS2MDL magnetometer, and an RTMC-G2-4IQ48 motion controller, making it suitable for robotics and real-time control applications. The design is organized into hierarchical schematics (power, configuration, user I/O) with custom symbols and footprints. It is licensed under CERN-OHL-P-2.0, allowing commercial use. Note: This is a hardware design repository, not software; the analysis criteria have been adapted accordingly.