$ show FPGAwars/icestudio
Icestudio is an open-source graphical FPGA design and programming environment. It allows users to create digital circuits by dragging, dropping, and wiring blocks representing logic elements, I/O, constants, memory, and code. The tool then compiles the design into Verilog, runs the open-source FPGA toolchain (yosys, nextpnr, apio) to generate a bitstream, and uploads it to a wide variety of Lattice iCE40 and ECP5 boards. The application is built as a desktop app using NW.js (Node.js + Chromium) with an AngularJS 1.x frontend, JointJS for diagramming, and a custom plugin system for extensibility. It supports over 60 FPGA boards, includes a package manager (iceHub) for block collections, a serial terminal plugin, a board editor, and an integrated toolchain shell. The codebase is mature but relies on several deprecated technologies (AngularJS, NW.js, Grunt) and lacks automated tests, making modernization risky. Key reusable elements include the event bus, plugin manager, orthogonal wire router, and file system indexer.
The LLM identified 5 files worth highlighting for reuse:
A generic publish/subscribe event bus with UUID-based filtering. Supports subscribing, publishing, and unsubscribing with optional wildcard channel prefixes. Isolated and could be extracted into any JavaScript project needing a decoupled event system.
Manages the full lifecycle of plugins: discovery via manifest files, installation, initialization, termination, and environment injection. Supports three plugin types (window, embedded, service) with shadow DOM isolation. Reusable pattern for any desktop application that needs a plugin system.
Custom Manhattan A* router for orthogonal wire routing in a graph editor. Uses a grid-based obstacle map with binary-search sorted set for efficient pathfinding. Implements direction handling and control-point adjustment. Could be extracted for any interactive schematic or wiring tool.
A filesystem abstraction that performs recursive directory scans and computes per-file signatures (mtime + size) to detect changes incrementally. Avoids re-reading unchanged files and supports pruning missing entries. Reusable for any application needing efficient file indexing with persistence.
A parser for FPGA constraint files in multiple formats (PCF, LPF, CST, XDC). Extracts pin assignments, IO standards, and timing constraints into a structured JSON object. Could be reused in other FPGA tooling or board definition editors without modification.