Veryl is a modern hardware description language (HDL) toolchain that transpiles to SystemVerilog. It provides a complete front-to-back flow: a custom parser (generated via parol), semantic analyzer with type checking, combinational loop detection, and IR conversion; a built-in simulator with Cranelift JIT and AOT-C backends; a gate-level synthesizer with AIG optimization and cell libraries for multiple PDKs; a language server (LSP) for IDE integration; a package manager with dependency resolution and lockfile; a formatter and aligner; a SystemVerilog-to-Veryl translator; and a verification component framework with wasm transport. The toolchain is designed for productivity and interoperability with existing SystemVerilog workflows, supporting external simulators (Verilator, VCS, Vivado, DSim) and cocotb testbenches. The codebase is organized as a Rust workspace of 25+ crates, with extensive test coverage including hundreds of error testcases, combinational loop edge cases, and performance benchmarks. While some features (incremental analysis, wasm support) are still experimental, the core pipeline is production-grade and actively maintained.
PeakRDL is a CLI toolchain for control/status register (CSR) generation centered around the SystemRDL 2.0 language. It compiles register descriptions from SystemRDL or imported formats (e.g., IP-XACT) and exports synthesizable SystemVerilog RTL, C headers, UVM register models, HTML documentation, and more. The architecture is a pluggable CLI: a core dispatcher loads subcommands (built-in: dump, globals, preprocess) and external exporter/importer plugins via setuptools entry points or TOML config. Input processing handles SystemRDL compilation, parameterized components, and element arrays. The codebase demonstrates strong Python engineering with modular configuration schema validation, argument file expansion with environment variable support, and a clean plugin discovery mechanism.