$ show veryl-lang/veryl
Veryl is a modern hardware description language (HDL) toolchain that transpiles to SystemVerilog. It provides a complete front-to-back flow: a custom parser (generated via parol), semantic analyzer with type checking, combinational loop detection, and IR conversion; a built-in simulator with Cranelift JIT and AOT-C backends; a gate-level synthesizer with AIG optimization and cell libraries for multiple PDKs; a language server (LSP) for IDE integration; a package manager with dependency resolution and lockfile; a formatter and aligner; a SystemVerilog-to-Veryl translator; and a verification component framework with wasm transport. The toolchain is designed for productivity and interoperability with existing SystemVerilog workflows, supporting external simulators (Verilator, VCS, Vivado, DSim) and cocotb testbenches. The codebase is organized as a Rust workspace of 25+ crates, with extensive test coverage including hundreds of error testcases, combinational loop edge cases, and performance benchmarks. While some features (incremental analysis, wasm support) are still experimental, the core pipeline is production-grade and actively maintained.
The LLM identified 6 files worth highlighting for reuse:
Implements a per-file fragment cache for incremental analysis. Captures and restores pass1 state (symbol table, definition table, etc.) using thread-local watermarks, ID rebasing, and postcard serialization. The pattern is reusable for any incremental compiler pass that needs to avoid re-parsing unchanged files while maintaining global ID consistency.
Defines a position relation algebra (AxisRelation) with composition, intersection, and piecewise-cover operations over finite integer ranges. Used for bit-level combinational loop detection but abstractly reusable for any static analysis that tracks dependencies between integer-indexed positions (e.g., array dataflow, register file analysis).
A Wadler-style pretty printer library with a generic Doc IR supporting Group, Line, Hardline, Anchored, and sourcemap anchors. Provides indentation, grouping, and fill-mode layout. Standalone and reusable for any code generation or formatting task requiring flexible, composable pretty-printing.
A single-flight cache for memoizing expensive combinational pipeline results. Uses Mutex+Condvar to coordinate multiple threads requesting the same computation, with a Slot enum (Idle/Computing/Done) to avoid redundant work. The pattern is reusable for any concurrent memoization scenario where the same key may be requested by multiple threads.
Implements DutReuseCache, a cross-testbench JIT compilation cache. Per-instance chunks are compiled once and reused across testbenches via a single-flight pattern with Mutex+Condvar. Uses structural fingerprints (XXH3-128) to detect equivalent IR across runs. The pattern is reusable for any JIT-based simulator or interpreter that wants to share compiled artifacts across multiple test cases.
Implements NPN4 canonicalization for 4-input Boolean functions, enumerating all AIG patterns up to 3 ANDs and storing minimal patterns per NPN class. Provides lookup_canonical and transform_pattern for cut-based rewriting. This is a research-grade logic synthesis technique, reusable for any AIG optimization or technology mapping that requires fast pattern matching on small cuts.