Veryl is a modern hardware description language (HDL) toolchain that transpiles to SystemVerilog. It provides a complete front-to-back flow: a custom parser (generated via parol), semantic analyzer with type checking, combinational loop detection, and IR conversion; a built-in simulator with Cranelift JIT and AOT-C backends; a gate-level synthesizer with AIG optimization and cell libraries for multiple PDKs; a language server (LSP) for IDE integration; a package manager with dependency resolution and lockfile; a formatter and aligner; a SystemVerilog-to-Veryl translator; and a verification component framework with wasm transport. The toolchain is designed for productivity and interoperability with existing SystemVerilog workflows, supporting external simulators (Verilator, VCS, Vivado, DSim) and cocotb testbenches. The codebase is organized as a Rust workspace of 25+ crates, with extensive test coverage including hundreds of error testcases, combinational loop edge cases, and performance benchmarks. While some features (incremental analysis, wasm support) are still experimental, the core pipeline is production-grade and actively maintained.
PeakRDL is a CLI toolchain for control/status register (CSR) generation centered around the SystemRDL 2.0 language. It compiles register descriptions from SystemRDL or imported formats (e.g., IP-XACT) and exports synthesizable SystemVerilog RTL, C headers, UVM register models, HTML documentation, and more. The architecture is a pluggable CLI: a core dispatcher loads subcommands (built-in: dump, globals, preprocess) and external exporter/importer plugins via setuptools entry points or TOML config. Input processing handles SystemRDL compilation, parameterized components, and element arrays. The codebase demonstrates strong Python engineering with modular configuration schema validation, argument file expansion with environment variable support, and a clean plugin discovery mechanism.
pConst/basic_verilog is a curated FPGA/ASIC RTL IP library, not a runnable application or service. In production use, engineers copy individual modules (Verilog/SystemVerilog) into their own FPGA designs. The core library consists of parameterized, synthesizable building blocks: clock-domain crossing (cdc_data.sv, cdc_strobe.sv), single-clock FIFOs and LIFOs (fifo_single_clock_ram.sv, fifo_single_clock_reg_v1/v2.sv, lifo.sv), UART TX/RX, SPI master, PWM/PDM modulators, debouncing, edge detection, pulse generation, Gray-code/one-hot/position encoders, PRBS generator/checker, and RAM/ROM templates. Nearly every module ships with a self-checking testbench and the modules are consistently parameterized and vendor-agnostic, with instantiation examples in header comments — this makes the root-level modules the highest-value, safest part of the repo to reuse. The file count is dominated by bundled third-party and vendor content: the Altera Advanced Synthesis Cookbook (2007-2011) with optimized CRC, AES, SHA, ECC, gearboxes, floating-point, and storage designs; Xilinx KCPSM6 PicoBlaze and PacoBlaze soft-processor distributions; a copy of the Xilinx board store XML for Vivado; AXI and Avalon master templates; and cross-vendor benchmark projects measuring Quartus/Vivado/Gowin/ISE compile throughput on a synthetic dynamic_delay design. These are valuable references but carry real technical drift (Altera Stratix II/IV primitives, Vivado 2018.x board metadata, hardcoded Quartus 20.x paths) and are not uniformly portable to modern toolchains. Engineering practice is solid for the personal-library genre: the repo is actively maintained (last commit March 2026), modules have clean parameter interfaces, and testbench coverage is extensive. Weaknesses are structural: no unified build system, no CI, duplicated equivalent modules (delay.v vs delay.sv, uart_rx.v vs uart_rx.sv) across the tree, and no dependency packaging. For an AI agent or engineer, this is best treated as a catalog of extractable, single-file RTL patterns rather than a system to integrate wholesale.