This is the ZJU ICICLES (浙江大学课程攻略共享计划) repository - a massive, student-maintained collection of course materials from Zhejiang University spanning 20+ academic disciplines. The repository contains lecture slides (PPT/PDF), lecture notes (Markdown/LaTeX/Typst), exam papers with solutions, homework assignments with code implementations, lab reports, textbook PDFs, and study guides. While classified as 'data_research' due to the presence of code artifacts in lab directories (compiler construction, data structures, operating systems, computer networks, digital logic), the dominant content is educational courseware - not a data pipeline or ML project. The repository serves as a knowledge base for ZJU students and demonstrates exceptional community curation. Key technical components include: a complete C compiler implementation (lex/yacc + codegen) in 编译原理/实验/, data structure implementations (red-black trees, graph algorithms, B-trees) in 数据结构基础/作业/dsHomework/, RISC-V OS lab code in 操作系统/ and 计算机组成与系统结构/, socket programming labs in 计算机网络/Lab/, and Verilog/FPGA code in 逻辑与计算机设计基础/ and 汇编与接口/. The repository is actively maintained with recent commits, but reproducibility of code artifacts is low due to course-specific dependencies, missing build configurations, and environment assumptions.
This repository provides educational materials for a hands-on course on building a RISC-V CPU core from scratch. The core is implemented in Transaction-Level Verilog (TL-Verilog) and is designed to run on the Makerchip online IDE. The repository contains a starting-point shell (risc-v_shell.tlv) with a simple test program that sums 1 to 9, and a reference solutions file (risc-v_solutions.tlv) that hides the full implementation. The library (lib/risc-v_shell_lib.tlv) includes reusable, parameterized components such as a register file, data memory, instruction decoder, ALU, and a sophisticated CPU visualization module. The code is modular, uses M4 macros for assembly and configuration, and is well-structured for educational purposes. While the repository is not a standalone application, it effectively demonstrates digital logic design and CPU microarchitecture concepts in a simulation environment.
This repository implements a complete 16-bit computer simulator built from fundamental logic gates (NAND, AND, OR, etc.) in Go. It includes a CPU, memory, ALU, memory-mapped I/O (keyboard and 240×160 pixel display), and a custom instruction set. The project provides three command-line tools: a simulator that loads binary programs and runs them with a GLFW-based graphical window, an assembler that converts a custom assembly language into binary, and a program generator that produces example assembly programs (e.g., text writer, sine wave animation, snake brush). The system is a faithful gate-level simulation—every component from bits to the CPU is wired together using Go structs, making it an educational tool for understanding computer architecture.