This repository provides educational materials for a hands-on course on building a RISC-V CPU core from scratch. The core is implemented in Transaction-Level Verilog (TL-Verilog) and is designed to run on the Makerchip online IDE. The repository contains a starting-point shell (risc-v_shell.tlv) with a simple test program that sums 1 to 9, and a reference solutions file (risc-v_solutions.tlv) that hides the full implementation. The library (lib/risc-v_shell_lib.tlv) includes reusable, parameterized components such as a register file, data memory, instruction decoder, ALU, and a sophisticated CPU visualization module. The code is modular, uses M4 macros for assembly and configuration, and is well-structured for educational purposes. While the repository is not a standalone application, it effectively demonstrates digital logic design and CPU microarchitecture concepts in a simulation environment.