$ show stevehoover/LF-Building-a-RISC-V-CPU-Core
This repository provides educational materials for a hands-on course on building a RISC-V CPU core from scratch. The core is implemented in Transaction-Level Verilog (TL-Verilog) and is designed to run on the Makerchip online IDE. The repository contains a starting-point shell (risc-v_shell.tlv) with a simple test program that sums 1 to 9, and a reference solutions file (risc-v_solutions.tlv) that hides the full implementation. The library (lib/risc-v_shell_lib.tlv) includes reusable, parameterized components such as a register file, data memory, instruction decoder, ALU, and a sophisticated CPU visualization module. The code is modular, uses M4 macros for assembly and configuration, and is well-structured for educational purposes. While the repository is not a standalone application, it effectively demonstrates digital logic design and CPU microarchitecture concepts in a simulation environment.
The LLM identified 3 files worth highlighting for reuse:
Implements a parameterized register file (rf) and data memory (dmem) in TL-Verilog. Both modules support configurable number of entries and data width, with read/write ports and integrated visualization. They are self-contained, can be instantiated in other TL-Verilog projects, and demonstrate good hardware design practices.
Provides a complex CPU visualization component (cpu_viz) that renders the instruction memory, decode stage, register file, and data memory in a canvas-based diagram. It animates data flow, highlights active signals, and displays missing signals for debugging. This component is highly reusable for any TL-Verilog CPU simulation.
Contains a test program (test_prog) that exercises each RV32I instruction (logical, arithmetic, shift, branch, jump, load/store) and checks results. It is parameterized and can be used as a regression test for RISC-V implementations. The assembly macros are generated via M4 and produce machine code automatically.