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$ show litex-hub/litex-boards

[account ↗] [repo ↗] APPLICATION ★ 500 371 ● active (last update 3 weeks ago)
reviewed by: deepseek/deepseek-v4-flash

This repository provides board support packages for the LiteX open-source FPGA SoC builder. It contains over 150 platform definitions (pinouts, connectors, toolchain setup) and corresponding target scripts that assemble a complete SoC (CPU, memory, peripherals) for each FPGA board. The architecture is a collection of Python modules organized into `litex_boards/platforms/` and `litex_boards/targets/`, with each target being a standalone script that can be invoked via `python -m litex_boards.targets.<board> --build --load`. The system supports a wide range of FPGA families (Xilinx, Lattice, Intel/Altera, Gowin, Efinix, CologneChip) and integrates with the broader LiteX ecosystem (LiteDRAM, LiteEth, LitePCIe, etc.) for memory controllers, networking, and high-speed interfaces. Key entry points are the `main()` functions in each target file, which use `LiteXArgumentParser` for CLI argument handling and `Builder` for bitstream generation. The repository is community-maintained under litex-hub and includes CI scripts for consistency checks, board inventory generation, and regression tests.

RATING7.7/10
QUALITY7.2/10
MAINTENANCEactive
DRIFTmedium
CONTRIBUTORS217
VELOCITY0.90
OPEN ISSUES43
CLOSED ISSUES124
LAST COMMIT3 weeks ago
Files by Type (count)
Python
537
Config
29
Markdown
6
YAML
3
Other (no ext)
2
Git Ignore
1
Other (.in)
1
TOML
1
Files by Type (size)
Python
3MB
Markdown
60KB
Other (no ext)
12KB
Config
12KB
YAML
3KB
Git Ignore
1KB
Other (.in)
124B
TOML
94B

The LLM identified 3 files worth highlighting for reuse:

A standalone Python script that audits all target files for consistent CLI option usage (e.g., default `--eth-ip`, mutual exclusion between `--with-etherbone` and `--eth-dynamic-ip`). It demonstrates a reusable pattern for enforcing conventions across a large collection of similar configuration files, and could be adapted for other multi-target projects.

file: .github/scripts/audit_board_consistency.py ↗ | tags: #consistency-check #ci-automation

Provides `OnChipOscillator` and `MFIOBasic` hardware modules for Intel/MicroFPGA boards. These are self-contained LiteX modules that abstract common on-chip oscillator and basic I/O functionality, reusable across multiple board targets without modification.

file: litex_boards/targets/microfpga/common.py ↗ | tags: #hardware-abstraction #reusable-module

Tests the flash image building process for Lattice iCE40, Muselab iCESugar, and Fomu boards. It validates the concatenation of bitstream and BIOS with proper padding and offset, demonstrating a reusable testing pattern for any FPGA board that requires custom flash image assembly.

file: test/test_flash_images.py ↗ | tags: #testing #binary-validation
Last analyzed: 2026-09-24 06:26:22.617114
Next check: 2026-10-01 06:26:22.613266
$ submit: