$ show lowRISC/ibex
Ibex is a production-quality open-source 32-bit RISC-V CPU core designed for embedded control applications. It provides a highly configurable, synthesizable core written in SystemVerilog with support for RISC-V ISA extensions (I, E, M, C, B) and security features like PMP, lockstep, and data-independent timing. The core features a modular architecture with separate functional units, a sophisticated configuration system via YAML/Python, and extensive verification infrastructure including UVM testbenches, formal proofs, and co-simulation with Spike ISS. It is actively maintained and used in real silicon designs including OpenTitan.
The LLM identified 3 files worth highlighting for reuse:
Generates FuseSoC configuration files from YAML definitions for the Ibex core. Handles complex parameter dependencies and validation. Demonstrates excellent hardware configuration management patterns that could be reused for other parameterizable IP blocks with minimal modification.
Centralized metadata handler for regression testing that collects build information, test results, and generates reports in multiple formats (HTML, JSON, JUnit, SVG). Features process-safe locking and clean separation of concerns. Could be extracted for use in other verification environments with minimal changes.
Orchestrates formal verification proofs using Yosys/rIC3 backend with support for parallel execution, strategy-based exploration, and result tracking. Manages proof strategies as JSON files and handles process lifecycle. Shows strong patterns for managing complex verification campaigns that could be adapted for other formal efforts.