Ibex is a production-quality open-source 32-bit RISC-V CPU core designed for embedded control applications. It provides a highly configurable, synthesizable core written in SystemVerilog with support for RISC-V ISA extensions (I, E, M, C, B) and security features like PMP, lockstep, and data-independent timing. The core features a modular architecture with separate functional units, a sophisticated configuration system via YAML/Python, and extensive verification infrastructure including UVM testbenches, formal proofs, and co-simulation with Spike ISS. It is actively maintained and used in real silicon designs including OpenTitan.