$ show Ralim/IronOS
IronOS is embedded firmware for a family of portable soldering irons (TS100, TS80/P, TS101, Pinecil, Pinecil V2, MHP30, Sequre S60/S60P/T55/S99). The firmware runs on three distinct SoC architectures — STM32F103 (Cortex-M3), GD32VF103 (RISC-V), and Bouffalo BL702 (RISC-V) — behind a single board-support abstraction. It implements PID temperature control of the soldering tip via PWM, thermocouple uV-to-temperature conversion with cold-junction compensation, USB-PD (FUSB302/FUSB302B/HUB238/FS2711) and Quick Charge 3.0 power negotiation, accelerometer/hall-effect-based motion detection for sleep, an OLED menu UI, and a full BLE GATT stack on Pinecil V2. The core control loop is: ADC samples tip thermocouple voltage (with PWM holdoff timing) -> gain/op-amp compensation and lookup-table interpolation to Celsius -> PID controller -> PWM duty to the heating element, with input voltage/current monitoring for wattage budgeting and thermal runaway protection.
The LLM identified 6 files worth highlighting for reuse:
Converts raw thermocouple ADC readings to Celsius using uV-vs-temperature lookup tables (Hakko, TS80, Pinecil variants), op-amp gain compensation, and cold-junction calibration. Based on an expired patent (US6087631A), self-contained with no internal coupling beyond a convert-temperature utility. Directly extractable into any project that reads a thermocouple through an ADC.
Defines the uniform BSP contract (power source detection, button scan, input voltage/handle temperature/tip resistance ADC reads, tip PWM control, flash save/load, watchdog, delay, reboot) implemented by five BSPs across three different ISAs and silicon vendors. Demonstrates a genuinely portable hardware abstraction pattern; the interface itself is reusable as a template for multi-target embedded products.
IRQ-driven I2C transaction engine built on FreeRTOS task notification: the ISR writes FIFO data, then releases the waiting task via semaphore and notification index rather than busy-polling. Handles non-multiple-of-4 byte edge cases and mutex-protects the bus. A clean, non-obvious pattern for low-level peripheral async I/O on single-core MCUs.
Schema-driven settings engineering: a YAML definition of every device setting (type, min/max/increment/default) drives C++ table generation at build time and binary/Intel-HEX settings image creation for offline editing via CLI. The model layer is self-contained (only depends on PyYAML and intelhex) and the YAML-to-codegen pattern transfers directly to other firmware/embedded projects.
Header-only fixed-size ring buffer template (history<T, SIZE>) plus a compile-time-weighted exponential moving average template (expMovingAverage<T, weighting>). Zero dependencies, usable in any C++ codebase needing lightweight streaming statistics without heap allocation.
Generic embedded helper library: linear and lookup-table interpolation, CRC32, and other stateless numerical utilities. The interpolation functions power NTC thermistor tables and tip calibration across all board variants; the CRC32 implementation is also used for device validation and BLE settings. Standalone and extractable into any firmware project.