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open-logic/open-logic ★ 1011 117 APPLICATION

This repository provides a library of reusable VHDL IP cores for FPGA design, focusing on fixed-point arithmetic, basic building blocks (FIFOs, RAM, clock crossing), and interfaces (SPI, I2C, UART, AXI). Each component is parameterized, well-documented, and includes testbenches for verification. The library is designed for portability across FPGA toolchains and includes tutorials for integration with major tools like Vivado, Quartus, and others.

RATING: 9.2/10 MAINT: active DRIFT: low
#vhdl-ip #fixed-point #fifo #clock-crossing #fpga-library
▸ 3 reusable components found
── end of results ──
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