This repository provides a library of reusable VHDL IP cores for FPGA design, focusing on fixed-point arithmetic, basic building blocks (FIFOs, RAM, clock crossing), and interfaces (SPI, I2C, UART, AXI). Each component is parameterized, well-documented, and includes testbenches for verification. The library is designed for portability across FPGA toolchains and includes tutorials for integration with major tools like Vivado, Quartus, and others.