thehardwarestore.ai

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── 99325 repos indexed ── | filtered by tag: #vhdl
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VHDL-LS/rust_hdl ★ 512 80 APPLICATION

This repository provides a comprehensive VHDL language toolchain written in Rust, centered around a Language Server Protocol (LSP) implementation. It includes a lossless concrete syntax tree (CST) parser (`vhdl_syntax`), a semantic analysis library (`vhdl_lang`) with name resolution, type checking, and overload resolution, a standalone linter (`vhdl-lint`) with rule selection and auto-fix, a formatter, and a CLI for AST dumping. The architecture is modular, with separate crates for parsing, analysis, linting, and the LSP server, enabling reuse of components like the CST framework and diagnostic system. The codebase demonstrates high craftsmanship with extensive test coverage (including fuzzing and snapshot tests), code generation from a grammar model, and careful handling of VHDL's Latin-1 encoding and source positions. However, it suffers from a dual-parser architecture (the older hand-written parser in `vhdl_lang` coexists with the newer CST parser in `vhdl_syntax`), which introduces duplication and potential drift. Some VHDL-2019 features are partially supported, and the project tracks the latest Rust stable, imposing a high maintenance burden. Overall, it is a production-quality tool for VHDL developers, with several reusable components that could be extracted for other VHDL tooling projects.

RATING: 8.2/10 MAINT: active DRIFT: medium
#vhdl #language-server #linter #parser #static-analysis #rust #ide-tool #cst #vhdl-parser #vhdl-language-server #rust-programming-language
▸ 5 reusable components found
MiSTer-devel/NES_MiSTer ★ 204 100 APPLICATION

This repository implements a cycle-accurate NES/Famicom console on FPGA, targeting the MiSTer platform. The core is written in Verilog/SystemVerilog with some VHDL, integrating a 6502 CPU (T65 core), PPU with composite video output, APU with expansion audio support, and dozens of cartridge mappers (MMC1-5, VRC1-7, FDS, Namco163, Sunsoft, etc.). It provides a complete hardware video/audio pipeline including scanlines, gamma correction, scandoubling, HQ2x scaling, and HDMI output. The system supports save states, cheat codes, zapper light gun, multiplayer adapters, and the Family BASIC keyboard. The codebase is well-structured with a modular mapper interface and a generic savestate bus pattern, though it is tightly coupled to the MiSTer platform (Cyclone V FPGA, HPS interface). It is an actively maintained core in the MiSTer ecosystem, with frequent releases and community contributions.

RATING: 8.1/10 MAINT: active DRIFT: low
#nes-emulation #mister-core #fpga #verilog #vhdl #retro-gaming #hardware-acceleration #ntsc-video
▸ 2 reusable components found
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