This repository implements a cycle-accurate NES/Famicom console on FPGA, targeting the MiSTer platform. The core is written in Verilog/SystemVerilog with some VHDL, integrating a 6502 CPU (T65 core), PPU with composite video output, APU with expansion audio support, and dozens of cartridge mappers (MMC1-5, VRC1-7, FDS, Namco163, Sunsoft, etc.). It provides a complete hardware video/audio pipeline including scanlines, gamma correction, scandoubling, HQ2x scaling, and HDMI output. The system supports save states, cheat codes, zapper light gun, multiplayer adapters, and the Family BASIC keyboard. The codebase is well-structured with a modular mapper interface and a generic savestate bus pattern, though it is tightly coupled to the MiSTer platform (Cyclone V FPGA, HPS interface). It is an actively maintained core in the MiSTer ecosystem, with frequent releases and community contributions.

The LLM identified 2 files worth highlighting for reuse: