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$ show VHDL-LS/rust_hdl

[account ↗] [repo ↗] APPLICATION ★ 512 80 ● active (last update 3 weeks ago)
reviewed by: deepseek/deepseek-v4-flash

This repository provides a comprehensive VHDL language toolchain written in Rust, centered around a Language Server Protocol (LSP) implementation. It includes a lossless concrete syntax tree (CST) parser (`vhdl_syntax`), a semantic analysis library (`vhdl_lang`) with name resolution, type checking, and overload resolution, a standalone linter (`vhdl-lint`) with rule selection and auto-fix, a formatter, and a CLI for AST dumping. The architecture is modular, with separate crates for parsing, analysis, linting, and the LSP server, enabling reuse of components like the CST framework and diagnostic system. The codebase demonstrates high craftsmanship with extensive test coverage (including fuzzing and snapshot tests), code generation from a grammar model, and careful handling of VHDL's Latin-1 encoding and source positions. However, it suffers from a dual-parser architecture (the older hand-written parser in `vhdl_lang` coexists with the newer CST parser in `vhdl_syntax`), which introduces duplication and potential drift. Some VHDL-2019 features are partially supported, and the project tracks the latest Rust stable, imposing a high maintenance burden. Overall, it is a production-quality tool for VHDL developers, with several reusable components that could be extracted for other VHDL tooling projects.

RATING8.2/10
QUALITY7.8/10
MAINTENANCEactive
DRIFTmedium
CONTRIBUTORS41
VELOCITY0.85
OPEN ISSUES84
CLOSED ISSUES203
LAST COMMIT3 weeks ago
Files by Type (count)
Other (.snap)
470
Rust
283
Other (.vhd)
57
Other (.vhdl)
34
TOML
23
Markdown
23
YAML
5
Git Ignore
3
Lock File
2
Python
2
Other (.ungram)
2
Docker Ignore
1
Files by Type (size)
Rust
4MB
Other (.vhdl)
2MB
Other (.snap)
314KB
Other (.png)
102KB
Other (.ungram)
67KB
Lock File
53KB
Markdown
45KB
Other (.vhd)
19KB
TOML
17KB
YAML
15KB
Other (.svg)
7KB
Other (.dict)
7KB

The LLM identified 5 files worth highlighting for reuse:

Implements the core concrete syntax tree (CST) with green/red tree pattern, trivia preservation, and a Rewriter API for lossless tree transformations. This is the foundation of the new parser and can be reused in any VHDL tool that needs to preserve whitespace and comments while manipulating the syntax tree.

file: vhdl_syntax/src/syntax/node.rs ↗ | tags: #lossless-cst #green-tree #rewriting

Provides a typed builder API for constructing VHDL syntax nodes programmatically, with domain-specific types like Identifier, AbstractLiteral, and BitStringLiteral. This enables programmatic generation of VHDL code (e.g., testbench generation) without dealing with raw tokens, and is decoupled from the parser.

file: vhdl_syntax/src/builder.rs ↗ | tags: #typed-builder #programmatic-ast

Implements a robust error recovery strategy for the parser using node layouts, follow sets, and a sync stack. It allows the parser to continue after syntax errors, producing a valid green tree with diagnostics. The recovery logic is parameterized by NodeKind and can be adapted to other grammars with similar layout descriptions.

file: vhdl_syntax/src/parser/error_recovery.rs ↗ | tags: #error-recovery #parser-resilience

Provides a Latin1Str type that handles VHDL's Latin-1 encoding with case-insensitive operations and safe UTF-8 conversion. This is a self-contained utility for any tool that needs to process VHDL source text with correct encoding semantics.

file: vhdl_syntax/src/latin_1.rs ↗ | tags: #encoding-aware-string #latin1

Implements SourceLocConverter, which converts byte offsets to line/column positions respecting source encoding (Latin-1, UTF-8) and target encoding (UTF-16 for LSP). This is a reusable component for any LSP server or editor tool that needs accurate position mapping.

file: vhdl_syntax/src/text/source_loc.rs ↗ | tags: #lsp-position-mapping #source-location
Last analyzed: 2026-09-22 11:51:12.971295
Next check: 2026-09-29 11:51:12.972291
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