libsystemctlm-soc is a SystemC/TLM-2.0 based library for hardware verification and co-simulation, primarily targeting Xilinx/AMD platforms. It provides a comprehensive framework for modeling, verifying, and testing AMBA-based protocols (AXI, ACE, CHI) and PCIe interfaces through traffic generation, protocol checking, and hardware/software bridging capabilities. The architecture is modular with clear separation between communication layers (libremote-port), platform-specific implementations (soc), protocol bridges (tlm-bridges), utility components (tlm-modules), traffic generators, and verification infrastructure. Rather than a standalone application, it functions as a reusable library/framework that engineers integrate into their verification environments to create testbenches for SoC designs, enabling co-simulation between CPU models (via QEMU) and FPGA/ASIC models.
PeakRDL is a CLI toolchain for control/status register (CSR) generation centered around the SystemRDL 2.0 language. It compiles register descriptions from SystemRDL or imported formats (e.g., IP-XACT) and exports synthesizable SystemVerilog RTL, C headers, UVM register models, HTML documentation, and more. The architecture is a pluggable CLI: a core dispatcher loads subcommands (built-in: dump, globals, preprocess) and external exporter/importer plugins via setuptools entry points or TOML config. Input processing handles SystemRDL compilation, parameterized components, and element arrays. The codebase demonstrates strong Python engineering with modular configuration schema validation, argument file expansion with environment variable support, and a clean plugin discovery mechanism.