$ show Xilinx/libsystemctlm-soc
libsystemctlm-soc is a SystemC/TLM-2.0 based library for hardware verification and co-simulation, primarily targeting Xilinx/AMD platforms. It provides a comprehensive framework for modeling, verifying, and testing AMBA-based protocols (AXI, ACE, CHI) and PCIe interfaces through traffic generation, protocol checking, and hardware/software bridging capabilities. The architecture is modular with clear separation between communication layers (libremote-port), platform-specific implementations (soc), protocol bridges (tlm-bridges), utility components (tlm-modules), traffic generators, and verification infrastructure. Rather than a standalone application, it functions as a reusable library/framework that engineers integrate into their verification environments to create testbenches for SoC designs, enabling co-simulation between CPU models (via QEMU) and FPGA/ASIC models.
The LLM identified 4 files worth highlighting for reuse:
Core QEMU-SystemC communication layer implementing a socket-based transaction protocol. Provides reusable middleware for connecting processor models (QEMU) with SystemC/TLM models through well-defined read/write interfaces. Demonstrates robust asynchronous communication handling with proper error recovery and could be extracted for other simulation environment coupling scenarios.
JSON-based traffic configuration system that separates test scenario definition from generation mechanism. Uses a facade pattern to provide simple interface for parsing traffic descriptions into executable test patterns. Highly reusable as it could be adapted to drive different stimulus generators with minimal changes, demonstrating clean separation of concerns in testbench design.
Generic register access API providing field-level manipulation capabilities through macros and functions. Completely protocol-agnostic, offering reusable hardware register modeling with support for read/write operations, field extraction, and insertion. Exemplifies clean abstraction for hardware interfaces that could be used in any register-based system without modification.
Template-based bridge implementing TLM-2.0 to AXI protocol conversion. Demonstrates consistent abstraction pattern used across all protocol bridges (AXI, ACE, CHI, etc.) with configurable bus widths and clear separation of transport and protocol layers. The template design makes it easily adaptable to other protocols while maintaining reusable core bridging logic.