This is a hardware/software co-design repository for the BSG Manycore accelerator, a tiled manycore processor with custom RISC-V RV32IMAF cores (vanilla_bean), a 2D mesh or ruche network-on-chip, and a multi-level memory hierarchy (local DMEM, shared DRAM via vcache). The software stack includes an SPMD programming model with a CUDA-like runtime, synchronization primitives (barriers, mutexes, MCS locks), and a library for remote memory access and tile-group operations. Extensive simulation and verification infrastructure is provided, including Verilator/VCS testbenches, profiling hooks (PC histograms, vcache stall analysis, energy estimation), and a Python analysis toolkit for trace and stats parsing. The repository targets both FPGA emulation and ASIC tapeout (multiple 16nm/12nm chips have been fabricated). While primarily a hardware platform, it also serves as an architecture research vehicle with microbenchmarks for performance and energy characterization. The codebase is well-structured but contains some deprecated directories and old toolchain patches, reflecting its research-group origins.