$ show bespoke-silicon-group/bsg_manycore
The BSG Manycore repository implements a tile-based manycore processor architecture with a complete hardware-software stack. It features a RISC-V based processor core, network-on-chip interconnect with mesh/ruche topologies, memory hierarchy including DMEM/DRAM/VCACHE, and synchronization primitives. The software stack includes a RISC-V toolchain, runtime libraries for SPMD programming, CUDA-like kernel interface, and numerous test programs and benchmarks. The repository demonstrates strong engineering practices with reusable components like the MCS mutex implementation, tile coordination primitives, and barrier synchronization mechanisms.
The LLM identified 7 files worth highlighting for reuse:
Implements the MCS (Mellor-Crummey & Scott) lock algorithm for scalable synchronization in manycore systems. Provides both C and assembly implementations for performance, showing consideration for low-level optimization while maintaining a clean interface.
Provides essential hardware abstraction for initializing tile coordinates (__bsg_x, __bsg_y, __bsg_id) which is fundamental to SPMD programming on this architecture. This small, focused utility could be used in any manycore program targeting the BSG Manycore architecture.
Defines the core interface for manycore programming including remote pointers, barrier synchronization, and memory operations. This is the main API that applications use to interact with the hardware, providing a clean abstraction over the underlying implementation.
Implements both software and hardware-assisted barriers for synchronizing groups of tiles. Shows consideration for different scales (tile-group vs chip-wide) with a clean interface featuring barrier.sync() method and supporting initialization functions.
Provides standard atomic operations (add, swap, etc.) needed for concurrent programming. Well-encapsulated with standard naming conventions, offering simple macro definitions that map to hardware instructions for safe concurrent access to shared memory.
Provides a familiar CUDA-like interface for writing parallel kernels, including grid/block dimensions, synchronization, and memory operations. Multiple kernel implementations (vector add, matrix multiply, etc.) demonstrate consistent patterns for GPU-style programming on manycore architecture.
Takes CSV trace data and generates visual 'blood graphs' showing instruction distribution over time for performance analysis. This self-contained tool could be adapted for other trace formats, with clear separation of concerns between data loading, processing, and visualization components.