Tilus is a tile-level GPU kernel programming language and compiler framework, primarily targeting NVIDIA architectures (SM80, SM90, SM100). It provides a Python DSL (`tilus.Script`) for writing high-performance CUDA kernels with explicit management of shared/register memory, tensor cores (WGMMA, tcgen05), and advanced synchronization primitives (mbarrier, cluster sync, TMA). The compiler stack includes a custom IR with layout inference (register/shared/tensor-memory), a pass pipeline (dead code elimination, bound-aware simplification, sub-byte type lowering), and backend emitters that generate PTX/CUDA code. Autotuning over tile sizes, warp counts, and pipeline stages is built into the framework. The architecture separates concerns into three layers: the user-facing `lang` package (Script, autotune, instructions), the `ir` package (tensors, layouts, instructions, inference rules), and the `backends` package (emitters, contexts, code generation). The `hidet` subpackage integrates a vendored copy of the Hidet IR and transforms, which provides the low-level expression/statement IR and a comprehensive set of optimization passes. Examples cover progressive matmul implementations (V0–V6) for Ampere, Hopper, and Blackwell, as well as flash attention, layer norm, and quantization kernels. This is a research project (ASPLOS '26 paper) with a strong emphasis on correctness and performance, evidenced by CUDA-level validation against PyTorch and cuBLAS. While the codebase is well-structured and demonstrates advanced compiler design patterns, it remains in beta (version 0.2.0) and carries some duplication between vendored Hidet code and native Tilus code, as well as hardware-specific constraints (NVGPU only). The layout inference system and autotuning infrastructure are particularly notable as reusable components.