$ show usbarmory/tamago
TamaGo is a bare-metal Go framework that enables running Go programs directly on hardware without an operating system or C runtime. It provides a modified Go runtime (GOOS=tamago) and a comprehensive set of drivers for ARM, ARM64, AMD64, RISC-V, and LoongArch architectures, covering SoCs from NXP, Raspberry Pi, SiFive, Microchip, Nuvoton, and others. The framework includes low-level initialization, exception handling, MMU, cache control, timers, interrupt controllers (GIC, LAPIC), and peripheral drivers for UART, I2C, SPI, USB device, Ethernet (ENET, gVNIC), SD/MMC, DMA, and cryptographic accelerators (CAAM, DCP). It also supports confidential computing features like AMD SEV-SNP and ARM TrustZone, as well as KVM paravirtualization with VirtIO and pvclock. The architecture is library-based: the `cmd/tamago` tool manages a custom Go distribution, while the runtime hooks (ramStart, printk, nanotime) are linked into Go via `go:linkname` from board and SoC packages. Each board package provides initialization functions that configure pin muxing, clocks, and peripherals. The code is production-grade, used in real projects like GoKey (smartcard), GoTEE (TEE), and ArmoredWitness. The repo is actively maintained, with a large number of supported platforms and a focus on security and minimal attack surface.
The LLM identified 6 files worth highlighting for reuse:
Provides a generic, first-fit DMA buffer allocator with region reservation, allocation, and deallocation. It is self-contained, used by multiple drivers (VirtIO, ENET, USB), and can be extracted into any project requiring contiguous physical memory allocation with alignment constraints.
Offers atomic read/write and bitfield manipulation for 32-bit memory-mapped registers. The pattern is extended to 8, 16, 64 bits and includes port I/O for AMD64. Each architecture has a dedicated assembly implementation. This is a foundational building block for hardware drivers and can be reused in any bare-metal or kernel project.
Implements the VirtIO split virtual queue with descriptor, available, and used rings. Handles buffer submission, completion notification, and queue synchronization. Isolated from transport-specific details (MMIO, PCI), making it reusable for any VirtIO device driver.
Provides a Deterministic Random Bit Generator (DRBG) based on AES-CTR with key erasure after each generation. It supports both hardware RNG hooks and a fallback software implementation. The design is self-contained and suitable for any system requiring cryptographically secure pseudo-random numbers.
Defines a complete USB device descriptor hierarchy with Device, Configuration, Interface, and Endpoint descriptors. Supports standard, CCID, CDC, and mass storage classes. The composition pattern is clean and extensible, reusable for any USB device implementation.
Defines a common MDIO/MIIM interface for Ethernet PHY drivers, with methods for read, write, reset, and link status. Concrete implementations for TI DP83825I and Microchip PHYs demonstrate the pattern. This abstraction can be reused across different SoC platforms with minimal adaptation.