$ show circuitnet/CircuitNet
The CircuitNet repository provides an open-source dataset and associated code for machine learning in Electronic Design Automation (EDA). It focuses on four key EDA tasks: congestion prediction, design rule check (DRC) prediction, IR drop prediction, and net delay prediction. The repository includes scripts for extracting features from LEF/DEF files (via Innovus output), training and evaluating deep learning models (CNNs and GNNs) for these tasks, and utilities for data loading and model training. The dataset is distributed in multiple versions (CircuitNet-N28, N14, N45) and consists of preprocessed features and labels stored as NumPy arrays. The codebase is organized into modular components: feature extraction, task-specific model directories, and shared utilities. While the repository enables reproduction of published results, it relies on specific tool versions (Innovus) and has hardcoded paths, which may require adaptation for reuse in different environments.
The LLM identified 3 files worth highlighting for reuse:
Parses LEF/DEF files to extract geometric and connectivity information. This standalone module solves the recurring problem of reading standard EDA layout files and can be reused in other EDA data processing pipelines with minimal adaptation.
Contains utility functions for geometric computations (e.g., coordinate transformations, area calculations) and feature engineering specific to physical design. These functions are isolated and can be extracted for use in other EDA-related feature extraction tasks.
Implements standard evaluation metrics for image-like predictions (NRMS, SSIM, EMD) used in the repository's EDA tasks. These metrics are general-purpose and can be reused in any image regression or segmentation task without modification.