$ show UF-Evan/DIJI-NES
DIJI-NES is a high-performance NES (Nintendo Entertainment System) emulator designed to run on the ESP32-S3 microcontroller. It emulates the 6502 CPU, PPU graphics, and APU audio with cycle-level accuracy, supporting mappers 0-4 (NROM, MMC1, UxROM, CNROM, MMC3). The system renders 256x240 pixel frames at near-60 FPS to an ST7789 display via LovyanGFX and outputs audio through an I2S DAC (MAX98357A). It features a dual-core architecture: Core 0 handles audio generation and display DMA, while Core 1 runs the emulation loop. The firmware includes a ROM browser menu, save/load state support, volume control, and a particle boot animation. The codebase demonstrates deep NES hardware knowledge and aggressive optimization for embedded systems, including IRAM placement, lookup tables, bank caching, and frame-skip logic. While the main application is tightly coupled to the ESP32-S3 platform, the core emulation components (CPU, PPU, APU, cartridge) are well-isolated and could be extracted for reuse in other NES emulation projects.
The LLM identified 4 files worth highlighting for reuse:
Full 6502 CPU emulation implementing all ~150 opcodes with optimized addressing modes, flag handling, and interrupt logic. Uses a deficit-tracking clock model (Anemoia-style) for efficient batch execution, a DRAM_ATTR cycle lookup table, and IRAM_ATTR on hot paths. Includes save state serialization. This component is self-contained (only depends on a bus interface via NES pointer) and could be extracted as a standalone 6502 emulator core for other projects.
NES APU emulation with four channels: two pulse waves (with duty cycle, envelope, sweep, length counter), triangle wave (with linear counter), and noise (LFSR-based). Implements frame counter (4-step/5-step modes), DC offset tracking, soft limiting, and volume control. Audio output is mixed and sent to I2S DAC via a dedicated FreeRTOS task. The component is well-documented with register maps and includes save state. It is self-contained and could be reused in other NES emulator projects.
NES PPU emulation with scanline-based background and sprite rendering. Features include: tile caching, OAM pre-evaluation (building sprite indices per scanline once per frame), branchless background pixel writes using 32-bit operations, packed 2bpp decode lookup table, and efficient Sprite 0 Hit detection. Supports 8x8 and 8x16 sprite modes, horizontal/vertical mirroring, and dynamic scrolling. The component is highly optimized for embedded systems with IRAM_ATTR and direct memory pointers. It is self-contained and could be extracted as a reusable PPU core.
Cartridge emulation handling iNES ROM loading, mapper logic for mappers 0-4 (NROM, MMC1, UxROM, CNROM, MMC3), and bank switching. Implements PRG bank offset caching, CHR bank pointer caching (8 x 1KB pointers for zero-overhead PPU access), nametable pointer caching for mirroring, and dirty iNES header detection. MMC3 IRQ is handled via scanline callbacks. Includes save state for all mapper state. This component is self-contained and demonstrates deep understanding of NES cartridge hardware; it could be reused in other emulators.